ros入门学习资料（详细）

这份代码本来是网上找的，但是是在很老的Qt版本下的，在qt5平台下运行失败。我已经移植好了，可以直接运行。

实现qt快速高效读取与写入excel。主要是供新手使用，我也是借鉴其他网友的代码，做了一些修改，更加适合新手学习使用。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

约200个Multisim仿真文件，有助于学习Multisim软件、学习电子线路基础知识

【实例简介】iar集成开发环境下开发的心电采集模块，采用ADS1298和MSP430分别作为采集芯片和控制芯片

2018电子设计大赛（TI杯）D题手势识别 全功能完成包括 划拳( 1 2 3 4 5 )和猜拳（石头剪子布）通过IIC通讯协议 对FDC2214 进行配置和读取通过限幅滤波 和中位数滤波法 对数据进行处理由TFT LCD 屏幕进行显示具有不错的学习价值。

python预测算整理集合,包含SVR回归预测详解及代码，AR/ARMA LSTM预测详解及代码 卡尔曼滤波，粒子滤波等算法

一个用C语言实现的FTP客户端，包含上传、下载、目录列表、删除、文件列表等功能。

旧手机制作电脑性能监视器，实时监视电脑性能，好玩DIY。包括adb-setup-1.3、aida64extreme_build_3744、Remote Panel_v1.16_apkpure.com、RemotePanelSetup以及两个配置好的设置文件，可直接使用。（附带教程链接）

110kV/10kV变电站电气一次部分设计，内含电气主接线图、电气总平面布置图、10kV配电装置布置图、110kV电气平面布置图、110kV出线间隔断面图、110kV主变压器及其进线间隔断面图、母线设备间隔断面图等等，内涵图纸全面，各种电气设施型号全面，欢迎广大毕业生与有需要人士下载，仅供参考。