Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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基于MFC的考试管理系统
该资源详细的讲解了怎样开发考试管理系统的步骤以及有大部分的代码资源。有利于学习开发、对照有关的系统开发。目录摘要…ABSTRACTII目录II第I章引言1开发背景…误!未定义书签。112选题意义误!未定义书签。113研究内容第2章系统的相关技术介绍…21MFC简介22 SQL SERVER2000简介423ODBC简介24 CRECORDSET类和 CRECORDVIEW类简介+“++++++++4+++25 POWERDESIGNER1简介24本章小结第3章系统的分析与设计.··中·“·::···········:··················“···:··*······3.1需求分析32系统设计321概要设计…非着丰非非目非非自83.2.2系统总体流程图…323系统模块设计,…324菜单设计.103.3本章小结…11第4章数据库设计4I数据库的需求分析124.2数据库表设计4.3数据库建表语句1344本章小结…19第5章系统实现205.1登录模块实现*····-··········*·=·····205.2基本信息模块实现1面错误!未定义书签。2052.1管理员信息…误!未定义书签。20522系部信息错误!未定义书签。24523班级信25524学生信错误!未定义书签。26525教师信息→·+“·*错误!未定义书签。275.2.6章节信息285.3题库管理模块实现.295.3.1判断题信息29532填空题信息*→··*→···········“····“=:··*····*······*·················“·533单选题信息…错误!未定义书签。30534多选题信息错误!未定义书签。3054试卷管理模块实现,…+++++++++++++++++++…误!未定义书签。31541定制试卷中··中中·和中·,···非中…{误!未定义书签。31542试卷管理错误!未定义书签。3455备份惨改模块实现.375.3.修改密码.5.32备份数据库13956本章小结日着南·前非非非非非第6章结束语.141致谢42参考文献43第1章引1.1开发背景在各学校开始逐步引入计算机的今天,试卷作为考察教学成果的重要手段之直没有得到较好的改善,试卷的编辑、整珥工作占了很大的工作量叫传统的手工出卷过程,存在不少弊端:◆出现不必要的重复劳动,造成人力资源及时间上的浪费:◆缺乏科学的衡量、评价及统一试卷难易度、试卷质量的有效手段;◆存在自教自考,考前漏题的情况◆试卷容易出现错漏缺现象,引起不必要的麻烦在以往的教学中,老师出试卷大多由手工出卷,这样生成的试卷往往会有知识点分布太集中、难易程度不当、分值分布不均等一些缺点;这样,既增加了老师的负担,也没有达到很好考查学生学习的真实水平,造成教学上的失误。基于以上的原因,有很多从事软件开发的人员,在试卷自动生成方面做了很大的研究。本系统希望利用计算杋强大的数据处理功能,由计算机逐步代替传统的人工出卷,并且规范岀卷程序,使出卷工作更加和学化、现代化,使教育工作更上一层楼。1.2选题意义w. docIn co考试管理系统,此课题目的是在我们以往学习数据库的基础上,灵活运用数据库开发软件C艹+和结构化查询语言SQL2000,开发出能供教学使用的一套出试卷系统,以方便教学。应用所学的有关数据库的知识,更深入地学习VC+和SQL200,将所学的书面知道和实际应用结合起来,以达到学以致用的日的。在各学校开始逐步引入计算机的今天,试卷作为考察教学成果的重要手段之·,通用试卷自动生成系统升化了传统的手工出卷,解决了很多问题,例如:遥免了不必要的重复劳动:节约了人力资源及时间;使用科学的衡量、评价及统一试卷难易度、试卷质量的有效手段;大幅度降低了试卷出现错漏缺的机率;减少不必要的麻烦。1.3开发内容班级考试管理系统主要涉及的信息数据包括系统管理员信息,系部信息,班级信息,学生信息,教师信息,试卷信息和各种题库等数据,涉及的操作主要包括各种信息数据的管理,为考试定制的试卷,试卷管理等管理操作,教师密码修改,备份数据库等。经考查与分析,典型的考试管理系统主要应具有以下功能:◆基本信息管理:包括对系统管理员信息,系部信息,班级信息,学生信息,救师信息,章节信息的录入,修改和删除等功能。◆试卷管理:包括对已创建的试卷数据的删狳,定制考试试卷,选择考试试卷等功能◆题库管理:包扦对判断题,填空题,单项选择题,多项选择题等题库的管理功能。QOc(m豆丁www.docin.com第2章系统的相关技术介绍21MFC介绍MFC( Microsoft Foundation Class Library)屮的各种类结合起来构成了一个应用程序框架,它的日的就是让程序员在此基础上来建立 Windows下的应用程序,这是一种相对SDK来说更为简单的方法。因为总体上,MFC框架定义了应用程序的轮廓,并提供了用户接口的标准实现方法,程序员所要做的就是通过预定义的接口把具体应用稈序特有的东西填入这个轮廓。 MicrosoftⅤ Visual c++提供了相应的工具来完成这个工作: App wizard可以用来生成初步的框架文件(代码和资源等);资源编辑器用于帮助直观地设计用户接口; Class wizard用来协助添加代码到框架文件;最后,编译,则通过类库实现了应用程序特定的逻辑3。MFC实现了对应用程序概念的封装,把类、类的继承、动态约束、类的关系和相互作用等封装起来。这样封装的结果对科序员来说,是一套开发模板(或者说模式)。针对不同的应用和目的,程序员采用不同的模板。例如,SD应用程序的模板,MDI应用程序的模板,规则DIL应用程序的模板,扩展DLL应用程序的模板, OLE ACTIVEX应用程序的模板,等等。这些模板都采用了以文档-视为中心的思想,每一个模板都包含一组特定的类。典型的MD应用程序的构成将在下节具体讨论。为了支持对应用程序概念的封装,MC内部必须作大量的作。例如,为了实现消息映射机制,M℃编程框架必须要保证首先得到消息,然后按既定的方法进行处理。又如,为了实现对DLL编程的支持和多线程编程的支持,MIFC内部使用了特别的处理方法,使用模块状态、线程状态等来管理一些重要信息。虽然,这些内部处理对程序员来说是透明的,但是,懂得和理解MFC内部机制有助于写出功能灵活而强大的程序。MFC借助C艹的优势为 Windows开发开辟了一片新天地,同时也借助 Application wizzard使开发者摆脱离」那些每次都必与基本代码,借助 Class Wizard和消息映射使丌发者摆脱了定义消息处理时那种混乱和冗长的代码段。更令人兴合的是利用C++的封装功能使开发者摆脱 Windows中各种句炳的困扰,只需要面对C+中的对象,这样一来使开发更接近开发语言而远离系统。正因为MFC是建立在C++的基础上,所以我强调CC+语言基础对开发的重要性。利用C++的封装性开发者可以更容易理解和操作各种窗口对象;利用C+的派生性开发者可以减少开发自定义窗口的时间和创造出可重用的代码:利用虚拟性可以在必要时更好的控制窗口的活动。而且C++本身所具备的超越C语言的特性都可以使开发者编写出更易用,更灵活的代码在MFC中对消息的处理利用了消息映射的方法,该方法的基础是宏定义实现,通过宏定义将消息分派到不同的成员函数进行处理。因此对于开发系统具有一定的优势。总之,MFC封装了Win32API, OLE APⅠ, ODBC API等底层函数的功能,并提供更高一层的接口,简化了 Windows编程。同时,MC攴持对底层API的直接调用。MFC提供了一个 Windows应用程序开发模式,对程序的控制主要是由MFC框架完成的,而且MFC也完成了大部分的功能,预定义或实现了许多事件和消息处理,等等。框架或者由其本身处理事件,不依赖程序员的代码;或者调用程序员的代码来处理应用稈序特定的事件。MFC是C++类库,程序员就是通过使用、继承和扩展适当的类来实现特定的目的。例如,继承时,应用程序特定的事件由程序员的派生类来处理,不感兴趣的山基类处理。实现这种功能的基础是C++对继承的支持对虚拟函数的支持,以及MFC实现的消息映射机制22 SQL SERVER2000介绍SQL( Structured Query Language,结构查询语言)是个功能强大的数据库语言。SQL通常使用于数据库的遥讯。ANS(美目国家标准学会)声称,SQL是关系数据库管理系统的标准话言。SQL语句通常用于完成一些数据库的操作任务,比如在数据庠中更新数据,或者从数据库中检索薮据。使用SQL的常见关系数据库管理系统有: Oracle、 Sybase、 Microsoft SQL Server、 Access, Ingres等等吊然绝大多数的数据库系统使用SQL,但是它们同样有它们自立另外的专有扩展功能用于它们的系统。但是,标准的SQL命令,比如" Select"、" Insert"、" Update"Delete"、" Create"和"Drop"常常被用于完成绝大多数数据库的操作但是,不像其它的语言,如C、 Pascal等,SOL没有循环结构(比如 if-then-lse、do- while以及函数定义等等的功能。而且SQL只有一个数据类型的固定设置,换句话说,你不能在使用其它编程语言的时候创建你自己的数据类型。SL功能强人,但是概括起来,它可以分成以下几组◆DML( Data Manipulation Language,数据操作语言):用于检索或者修改数据◆DDL( Data Definition Language,数据定义语言):用于定义数据的结构,比如创建、修改或者删除数据库对象;◆DCI.( Data Control Language,数据控制语言):用于定义数据库用户的杈限DML组可以细分为以下的几个语句:◆ SELECT:用于检索数据。◆ INSERT:用于增加数据到数据库。◆ UPDATE:用于从数据库中修改现存的数据。◆ DELETE:用于从数据库中删除数据23ODBC介绍ODBC( Open Database Connectivity,开放数据库互连)是微软公司开放服务结构(WOSA, Windows Open Services Architecture)中有关数据库的一个组成部分,它建立了一组规范,并提供了一组对薮据庳访问的标准API(应用程序编程接口)。这些AP利用SQL来完成其大部分任务。ODBC本身也提供了对SQL语言的支持,用户可以直接将SQL语句送给ODBC。一个基于ODBC的应用程序对数据库的操作不依赖任何DBMS,不直接与DBMS打父道,所有的数据库操作由对应的DBMS的ODBC驱动程序完成。也就是说,不论是 FoxPro、Aes, MYSQL还是Oracle数据库,均可用 ODBC AP进行访问。由此可见,ODBC的最大优点是能以统一的方式处理所有的数据库。一个完整的ODBC由下列几个部件组成:应用程序( Application)ODBC管理器( Administrator),该程序位于 Windows95控制面板( Control Panel)的32位ODBC内,其主要任务是管理安装的ODBC驱动程序和管理数据源。驱动程序管理器 Driver Manager)。驱动程序管理器包含在ODBC32DLL中,对用户是透明的。其任务是管理ODBC驱动程序,是ODBC中最重要的部件数据源。数据源包含∫数据库位置和数据库类型等信息,实际上是一种数据逹接的抽象。应用程序要汸问一个数据库,首先必须用ODBC管理器注册一个数据源,管理器根据数据源提供的数据厍位置、数据厍类型及ODBC驱动程序笭信息,建立起ODBC与貝体数据库的联系.这样,只要应用程序将数据源名提供给ODBC,ODBC就能建立起与相应数据库的连接。在ODBC中, ODBC API不能直接访问数据库,必须通过驱动稈序管理器与数据库交换信息。驱动程序管理器负责将应月程序对 ODBC API的调用传递给正确的驱动程序,而驱动程序在执行完相应的操作后,将结果通过驱动程序管理器返回给应用程序。在访问ODBC数据源时需要ODBC驱动程序的支持,用 Visual++6.0安装程序可以安装SQLServer、 Access、 Paradox、 dBase、 FoxPro、 Excel、 Oracle和 Microsoft Text等驱动程序.在缺省情况下,VC6.0只会安装 SQL Server、 Access、 FoxPro和d Base的驱动程序.如果用户需要安装别的驱动程序,则需要重新运行VC6.0的安装程序并选择所需的驱动程序。ODBC使用层次的方法来管理数据厍,在数据库通信结构的每一层,对可能出现依赖数据库产品自身特性的地方,ODBC都引入一个公共接口以解决潜在的不一致性,从而很好地解决了基于数据库系统应用程序的相对独立性,这也是ODBC一绎推出就获得巨大成功的重要原因之一。24 CRecordSet类和 CRecord View类CRecordset对象代表从一个数据源选择的一组记录的集合,被称作“记录集”。CRecordset对象可以以两种形式使用:动态集和快照。动态集是与其它用户的数据更新保持同步的动态数据集。快照是数据的静态视图。每一种形式都代表打开记录集吋定的组记录,但是当滚动到动态集中的个记录时,动态集将反怏后来由其它用户或由应用程序巾其它记录集对此记录所做的改变。要使用任何一种记录集,通常需要从 CRecordset派生一个应用程序指定的记录集类。记录集从一个数据源中选择记录,然后用户就可以◆在这些记录中滚动更新记录并指定一种加锁模式。过滤记录集,以获得那些从数据源中选择出来的可利用的记录排序记录集。◆参数化该记录集以定制它的具有要直到运行时才知道的信息的选项。CRecord view对象是在控件中显小数据库记录的视这种视是一种直接连接到一个〔 Recordset对象上的格式视。此视是从一个对话框模板资源创建的,并将CRecordSet对象的字段显示在对话框模板的控件中。 CRecordview对象利用对话框数据交换(DDX)和记录字段交换(RFX)机制,使格式上的控件和记录集的
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