系统辨识大牛Ljung编写的MATLAB系统辨识使用手册
系统辨识大牛Ljung编写的MATLAB系统辨识使用手册，这本书详细地介绍了在MATLAB已经所属simulink环境下，系统辨识工具箱的一些使用办法，是一本非常经典的教材！Revision Historypril 1988First printingJuly 1991Second printingMay1995Third printingNovember 2000 Fourth printingRevised for Version 5.0(Release 12)pril 2001Fifth printingJuly 2002Online onlyRevised for Version 5.0.2 Release 13)June 2004Sixth printingRevised for Version 6.0.1(Release 14)March 2005Online onlyRevised for Version 6.1.1Release 14SP2)September 2005 Seventh printingRevised for Version 6.1.2(Release 14SP3)March 2006Online onlyRevised for Version 6.1.3(Release 2006a)September 2006 Online onlyRevised for Version 6.2 Release 2006b)March 2007Online onlyRevised for Version 7.0 ( Release 2007a)September 2007 Online onlyRevised for Version 7.1 (Release 2007bMarch 2008Online onlyRevised for Version 7.2(Release 2008a)October 2008Online onlyRevised for Version 7.2.1 Release 2008b)March 2009Online onlyRevised for Version 7.3(Release 2009a)September 2009 Online onlyRevised for Version 7.3.1(Release 2009b)March 2010Online onlyRevised for Version 7. 4 (Release 2010a)eptember2010 Online onlyRevised for Version 7.4.1(Release 2010b)pril 2011Online onlRevised for Version 7.4.2(Release 2011a)September 2011 Online onlyRevised for Version 7.4.3(Release 2011b)March 2012Online onlyRevised for Version 8.0( Release 2012aabout the DevelopersAbout the Developersystem Identification Toolbox software is developed in association with thefollowing leading researchers in the system identification fieldLennart Ljung. Professor Lennart Ljung is with the department ofElectrical Engineering at Linkoping University in Sweden. He is a recognizedleader in system identification and has published numerous papers and booksin this areaQinghua Zhang. Dr. Qinghua Zhang is a researcher at Institut Nationalde recherche en Informatique et en Automatique(INria) and at Institut deRecherche en Informatique et systemes Aleatoires (Irisa), both in rennesFrance. He conducts research in the areas of nonlinear system identificationfault diagnosis, and signal processing with applications in the fields of energyautomotive, and biomedical systemsPeter Lindskog. Dr. Peter Lindskog is employed by nira dynamiAB, Sweden. He conducts research in the areas of system identificationsignal processing, and automatic control with a focus on vehicle industryapplicationsAnatoli Juditsky. Professor Anatoli Juditsky is with the laboratoire JeanKuntzmann at the Universite Joseph Fourier, Grenoble, france. He conductsresearch in the areas of nonparametric statistics, system identification, andstochastic optimizationAbout the developersContentsChoosing Your System Identification ApproachLinear model structures1-2What Are Model objects?Model objects represent linear systemsAbout model data1-5Types of Model objectsDynamic System Models1-9Numeric Models1-11umeric Linear Time Invariant (LTD Models1-11Identified LTI modelsIdentified Nonlinear models1-12Nonlinear model structures1-13Recommended Model Estimation Sequence1-14Supported Models for Time- and Frequency-DomainData,,,,,,,1-16Supported Models for Time-Domain Data1-16Supported Models for Frequency-Domain Data1-17See also1-18Supported Continuous-and Discrete-Time Models1-19Model estimation commands1-21Creating Model Structures at the command Line ... 1-22about system Identification Toolbox Model Objects ... 1-22When to Construct a Model Structure Independently ofEstimation1-23Commands for Constructing Model Structures1-24Model Properties1-25See als1-27Modeling Multiple-Output Systems ......... 1-28About Modeling multiple-Output Systems1-28Modeling Multiple Outputs Directly1-29Modeling multiple outputs as a Combination ofSingle-Output Models.......1-29Improving Multiple-Output Estimation Results byWeighing Outputs During Estimation ....... 1-30Identified linear Time-Invariant models1-32IDLTI Models1-32Configuration of the Structure of Measured and Noise oRepresentation of the Measured and noise Components foVarious model Types1-33Components ....1-35Imposing Constraints on the Values of ModeParameters1-37Estimation of Linear models1-8Data Import and Processing2「Supported Data ...2-3Ways to Obtain Identification DataWays to Prepare Data for System Identification ... 2-6Requirements on Data SamplingRepresenting Data in MATLAB Workspace·····Time-Domain Data Representation2-9Time-Series Data Representation2-10ContentsFrequency-Domain Data Representation ....... 2-11Importing Data into the Gui2-17Types of Data You Can import into the GUi2-17Importing time-Domain Data into the GUI2-18Importing Frequency-Domain Data into the GUI2-22Importing Data Objects into the GUI ......... 2-30Specifying the data sampling interval2-34Specifying estimation and validation Data2-35Preping data Using Quick StartCreating Data Sets from a Subset of Signal Channelo2-362-37Creating multiexperiment Data Sets in the gUi2-39Managing data in the gui ............. 2-46Representing Time- and Frequency-Domain Data Usingiddata object2-55iddata constructor2-55iddata Properties.........2-58Creating Multiexperiment Data at the Command Line .. 2-61Select Data Channels, I/O Data and Experiments in iddataObjects2-63Increasing Number of Channels or Data Points of iddataObjects2-67Managing iddata Objects2-69Representing Frequency-Response Data Using idfrdObiec2-76idfrd Constructor2-76idfrd Properties2-77Select I/o Channels and Data in idfrd Objects ..... 2-79Adding Input or Output Channels in idfrd Objects2-80Managing idfrd Objects2-83Operations That Create idfrd Objects2-83Analyzing Data quality2-85Is your data ready for modeling?2-85Plotting Data in the guI Versus at the command line2-86How to plot data in the gui2-86How to plot data at the command line2-92How to Analyze Data Using the advice Command2-94Selecting Subsets of Data2-96IXWhy Select Subsets of Data?2-96Extract Subsets of Data Using the GUI2-97Extract Subsets of data at the Command Line2-99Handling Missing Data and outliers2-100Handling missing data2-100Handling outliers2-101Extract and Model Specific Data Segments2-102See also2-103Handling offsets and Trends in Data2-104When to detrend data2-104Alternatives for Detrending Data in GUi or at theCommand-Line2-105Next Steps After detrending2-107How to Detrend Data Using the Gui2-108How to detrend data at the Command line2-109Detrending Steady-State Dat109cending transient Dat2-109See also2-110Resampling Data2-111What Is resampling?...,,.,,,,,,,,,,,.2-111Resampling data without Aliasing Effects2-112See also2-116Resampling data Using the GUi.,,,,2-117Resampling Data at the Command line2-118Filtering Data2-120Supported Filters2-120Choosing to Prefilter Your Data2-120See also2-121How to Filter Data Using the gui2-122Filtering Time-Domain Data in the GuI........ 2-122Content
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altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
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