完整的OFDM通信系统的仿真设计，包括编码，调制，IFFT，

基于MATLAB／Simulink的光伏电池建模与仿真

RTKLIB是日本东京海洋大学开发（Tokyo University of Marine Science and Technology）开发的一个开放源程序包，供标准与精确GNSS全球导航卫星系统应用。RTKLIB包括一个可移植的程序库和几个应用程序（AP）库。RTKLIB的特点：（1）支持标准的和精确的定位算法：GPS，GLONASS，QZSS准天顶卫星系统,北斗和SBAS（2）支持多种定位模式与GNSS实时和后处理：单点，DGPS / DGNSS，动态的，静态的，移动基线，定点，PPP运动，PPP静态和PPP定点（3）支持多种标准格式和协议GNSS：RINEX 2.10，2.

好用的snmp测试工具，测试SNMP设备及系统SNMP必备工具

针对认知无线电中空闲频谱资源的最优分配问题，分别采用了遗传算法和粒子群算法进行求解。该代码是利用遗传算法和粒子群算法求解该问题的matlab仿真代码。

基于FPGA的高频PWM开关电源控制器设计,基于FPGA的DC／DC数字控制器中A／D采样控制、数字PI算法的实现；重点描述了采用混合PWM方法实现高分辨率、高精度数字PWM的设计方案

索尼PS2手柄破解协议例程 STM32 keil环境 ps2遥控小车,舵机,手柄震动.

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

无线定位基本算法，其中包括了chan算法、Taylor算法、Tdoa

华科电机学课后答案--辜承林 1-6章都有非常好

具有自学习和自适应能力的单神经元自适应PID控制算法