OTSU算法二维matlab实现

【优质资源】（资源整理自王道以及２０１８CS考研劝退，若有侵权删，很感谢学长学姐对于我考研的帮助，此次自己也是把复试资料认真整理一遍，希望能对志在考南大CS的学弟学妹有所帮助）内容包括离散数学和编译原理南大老师的全部课件，／＊＊—＞最重要的文件是近十年的离散数学和编译原理的真题＜—＊＊／，还有一份面试真题总结，以及上机提示以及上机题目整理，都是帮助我复试非常有用的文件，另外还有一份南京大学计算机系计算机技术专业硕士研究生培养方案以及１７年录取分数参考，希望对学弟学妹也有所帮助蟹蟹支持o(*￣▽￣*)ブ／＊＊第二次补充＊＊／谢提醒，补充了２００９－２０１４南大上机试题，指定上机书目的课后习

基于Matlab的改进人工势场法路径规划与避障实验验证。

labview汽车仪表盘

仿VS编辑界面，采用反射机制

altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation

设信道响应已知。采用线性模型下的线性MMSE估计方法，根据观测信号yk估计发送信号xk。

检测估计和调制理论作者简介　　Harry L.Van Trees 美国麻省理工学院电子工程系教授，曾担任美国空军首席科学家、美国国防通信署首席科学家等要职。 　迄今为止，本书仍然是公认的关于检测、参数估计和线性与非线性调制波形估计方面的一本论述详尽、深入、成功的著作。也是一本较好的研究生教材。内容是研究发生在通信、雷达和声纳中被噪声污染了的各种线性与非线性调制、随机与非随机波形的最佳处理的数学方法和物理结构，各种系统可能达到的性能极限和影响它的各种因素。全书包括导论、经典检测和估计理论、随机过程的描述、信号检测与信号参数估计、连续波估计、线性估计和讨论等7章。每章附有相当数量的扩大内容

详尽介绍西门子组态软件安装、功能、及使用，SIEMENSVolume 1前言系统概述2SIMATIC HM授权3Wincc手册Wincc资源管理器4概述5常规信息6第一册用户管理器7Volume 2图形编辑器8报誓记录9变量记录10文本库全局脚本12订货号:6AV6392-1XA05-0BA1交叉索引13Winco°、 SIMATIC°、S|NEC°、STEP°是西门子注册商标木手册中所有其它的产品和系统名称是(注册的)其各自拥有者的商标,必须被相应地对待。(若没有快速写入权限,不允许对本文件或其内容迂行复制、传送或(我们已检查了本手册的内容,使其与硬仁和软件所擢述使用的相致。由于不可能完全消除差错,我们也不能保证完违犯老将要对损坏负责任。保留所有板利,包括由专利授权创建的权全的一致性。然而,本手册中的数据是经常规检查的,在利,对实用新型或设计的注册。)以后的版本中包括了必要的修正。欢迎给我们提出建议以便改进。)SIemens AG1994-2000保留所有权利改变的技术数据前言目的Winco用户指南描述:Wincc的结构、功能及其组件如何建立指定系统的 Winco项目如何在运行系统中使用 Wincc该用户指南适用于 WinCc v5。信息编排该用户指南是 SIMAIIC HM文档的一部分。下面列出了所有 Win cc文档。安装基砧基本组态手册通讯手册通道文档用户归档Pro Agent冗余户札服务器基本过程控制过程控制过程控制运行系统道道支持于发商具箱工具刖舌文档目录入门组态实例引导初学者按步骤执行项目,并全面介绍了 Win cC的功能。Wincc v5提供以下信息第一册Wincc中的相互联系系统总览软件保护●软件保护如何发挥作用控制中心●操作结构、方法和使用 Wincc资源管理器服务器数据变量和变量组通道CC和过程之间的通讯报表编辑器●在报表编辑器中创建和编辑打印布局用户管理员在用户管理员中分配用户权限第二册●在图形编辑器中生成过程映射图形编辑器在报警记录中组态、处理和归档消息报警记录●在变量记录中组态、处理和归档测量值变量记录文本库在文本库中组态多种语言文本全局脚本在全局脚本中编译C函数和动作交叉索引用交叉索引生成交叉索引列表组态手册提供以卜信息册举例说明在 Wincc中组态组态的特殊方面脚本、C函数和动作(C教程)的开发环境全局库中的图形对象通讯手册提供以下信息册通过 PROFIBUS、工业以太网和OPC链接到S|MATC通讯驱动程序以及通过实例说明如何组态驱动程序●组态的特殊方面通道描述提供通讯驱动程序信息在自动系统中寻址变量为通讯伙伴设置参数前言文档‖目录Winco选项提供选项信息用户归档用户归档:创建和使用用户归档客户机服务器●客户机服务器:客户机/服务器系统中WnCC的结构和冗余使用●冗余:冗余系统的结构和使用ProAgent提供 ProAgent选项(过程诊断)信息如何组态系统过程诊断如何追踪过程错误并识别其原因基本过程控制提供 Wincc过程控制选项信息存储●画面树管理器分屏管理器芯片卡设备状态监控视频●时间同步过程控制运行系统提供WnCC过程控制选项信息●运行系统操作开放式开发商工具箱说明程序员如何使用WmCc的AP功能以及如何访间数据通道开发商工具箱说明如何开发将 Winco连接到任一目标系统的通讯驱动程刖舌附加支持如果在操作中遇到问题请立即与我们联系。如果在解决问题中需要帮助,请拨49911895-7000。记住于头备有软件|号:该号码在软件产品卡中如果授权夭失或损坏,请通过电话与客户支持部联系,以便“修复”授权。电话号码是+49911895-7200。SIMATIC产品信息S|MATC客户支持部通过在线服务提供广泛的 SIMATIC产品附加信息:用户可获得常规最新信息通过Internethttp://www.ad.siemenscom/wincc通过传真号码+4987659302779500对操作可能有所帮助的最新产品信息和下载信息:iliidInternethttp://www.ad.siemens.de/support/htm1-00/index.shtm1通过纽伦堡电子公告牌系统 SIMATIC客户支持信箱):号码是+49911895-7100若需要拨号进入我们的信箱,请使用最高波特率不超过28,800bps(也就是说至多∨34)的调制解调器,并将其参数设置为8、N、1、ANS|,或通过|SDN(×75,64KB)拨号进入。SIEMENSVolume 1前言系统概述2SIMATIC HM授权3Wincc手册Wincc资源管理器4概述5常规信息6第一册用户管理器7Volume 2图形编辑器8报誓记录9变量记录10文本库全局脚本12订货号:6AV6392-1XA05-0BA1交叉索引13Winco°、 SIMATIC°、S|NEC°、STEP°是西门子注册商标木手册中所有其它的产品和系统名称是(注册的)其各自拥有者的商标,必须被相应地对待。(若没有快速写入权限,不允许对本文件或其内容迂行复制、传送或(我们已检查了本手册的内容,使其与硬仁和软件所擢述使用的相致。由于不可能完全消除差错,我们也不能保证完违犯老将要对损坏负责任。保留所有板利,包括由专利授权创建的权全的一致性。然而,本手册中的数据是经常规检查的,在利,对实用新型或设计的注册。)以后的版本中包括了必要的修正。欢迎给我们提出建议以便改进。)SIemens AG1994-2000保留所有权利改变的技术数据

虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器虚拟示波器

TWINCAT PLC 编 程 手 册