1553B中文手册
恩菲特公司的1553B中文手册，手册丰富，详细，是1553B开发者的优选方案成都恩菲特科長有限公司EPH31580日录恩菲特产品保修条款…安全标志符号,D香看看看。。。垂垂看导D看警告第1章芯片概述…11.简介12.EPH31580特性111.3.EPH31580描述……14.电气特性+++··+++++++.1415.功能描述.…1.6.曼彻斯特解码…171.7.吋间戳178.中断19.存储器访问和寄存器访问1.10. BUS CONTROL框架.171.11. REMOTE TERMINAL框架……11.12. BUS MONITOR框榘18第2章软件接口自●●看命·●●●看鲁●息1921.上电状态22.存储器管理23.寄存器定义…21.中断屏敞寄存器(读/写22.配置寄冇器#1(读/23.配置寄存器#2(读/写)24.开始/复位寄存器(写)2.5.BC/RT命令堆栈指针寄存器(读)….262.6.BC控制字尕RT子地址控制宇寄存器(读)…2627.时标寄存器(读/写)28.中断状态寄存器(读29.配置寄存器#3(读/写)……2.10.配置寄冇器#4(读/写)21.配置寄存器#5(读/写)2.12.数据堆栈指针寄存器(读)…322.13.BC下一条消息开始时间寄存器(读/)214.BC帧时间/RT最后一个命令字/BM触发设置寄存器(读/写)2.15.RT状态字寄存器(读)216.RIB字寄存器(读).342.17. BLOCK STATUS WORD第3章 BUS CONTROL OPERATION……38HTTP:www.enpht.comTel:028-851482738528FAX:028-85148287107第3页成都恩菲特科長有限公司EPH31580BC存储器管理…38ACTIVE AREAS DOUBLE BUFFERING38PROGRAMMING OF BC MESSAGE FRAMES39BC Memory managcmcntMessage Block Formats∴39BC控制字∴…42DESCRIPTOR STACK44C MESSAGE GAP TIMEBC FRAME AUTO REPEATMINOR AND MAJOR FRAMES甲甲···:·…46BCⅠ NTERRUPT……46OTUER FUNCTIONBC SOFTWARE INITIALIZATION SEQUENCE··47BC PSEUDO CODE EXAMPLE.49第4章 REMOTE TERMINAL OPERATION,51RT存储器结构51RT存储器管理SUBADDRESS CONTROL WORDRT STACK AND INTERRUPTSTIME TAG WORDDATA BLOCK POINTER OR MODE DATA WORD57COMMAND WORD RECEIVEDRT COMMAND ILLEGALIZATION57SELECTED MODE CODE INTERRUPT60BROADCAST OPT⊥0NBUSY BITRT ADDRESS INPUTS62RT STATUS WORDRT-TO-RT RESPONSE TIMEOUT64SUMMARY OF RESPONSES TO MODE CODE MESSAGESRT SOFTWARE INITIALIZATION PROCEDURERT PSEUDO CODE EXAMPLE.68第5章 BUS MONITOR OPERATION.71MONITUR SELECTION FUNCTIONMESSAGE MONITOR FORMATSBM存储器管理MESSAGE MONITOR BLOCK STATUS WORDBM SOFTWARE INITIALIZATION PROCEDURE,76第6章 EXTERNAL INTERFACES通垂函a看自PIN DESCRIPTIONS BY FUNCTIONAL GROUPS隔离变压器到外部系统的连接BUFFERED u TRANSPARENT MODEHTTP:w.enphtcomTEL:028-851482738528FAX:028-85148287107第4页成都恩菲特科長有限公司EPH31580外部时序接口BUFFERED模式接口时序85与几和典型器件的连接与ADSP2101的连接与68040的连接与80286的连接.环境温度封装形式…订货号附录一:变压器选型手册97HTTP:/ww.enphtcomTEL:028-85148273/8528FAX:028-85148287107第5页成都恩菲特科長有限公司EPH31580恩菲特产品保修条款产品名称:1553A/B协议芯片产品型号:EP-H31580保修期限:一年1.恩菲特公司对由恩菲特公司出售的硬件产品和附件提供质量保修,保修期限如上所示。在保修期内如果出现因质量原因而产生故障,恩菲特公司在收到关于产品故障的通知并经查验核实后,有权选择维修或整套更换产品。整套更换的产品可以是新的或接近新的2.恩菲特公司保证软件产品经过充分测试。如果恩菲特公司在保修期内收到关于软件故障的通知,将在查验核实后免费更换软件3.恩菲特公司不保证在产品修理过程中产品可不中断地使用。但恩菲特公司保证在合理的期限内修理好发生故障的产品4.产品保修期从产品发运之日或由恩菲特公司开始安装之日起开始计算。如果用户的进度安排延后使恩菲特公司在产品发运之日起30天内仍未开始安装,产品保修期从交付之日后的笫31天开始计算5.恩菲特公司对任何下列情况而导致的产品故障和损坏不提供免费保修:(a)错误的使用或不适当的维护和校正,(b)非恩菲特公司提供的软件、接口、部件或其它物品,(c)未经许可的拆卸、修改和错误使用,(a)超过产品技术规格指明的范围使用,(e)不适当的运输、搬运和存贮,(f)其它不可抗力原因造成的故障或损坏(如HTTP:ww.enphtcomTEL:028-851482738528FAX:028-85148287107第6页成都恩菲特科長有限公司EPH31580地震、战争、交通事故等)6.在法律允许的范围内,上述保修条款是唯一明确的,同时没有任何其它的保修条款,不论是书面的或口头的。恩菲特公司明确表示拒绝承认任何暗示的保修条款和商业条款7.如果用户因使用恩菲特公司产品造成对其它物品损坏或身体伤害,经法院裁定其直接原因是恩菲特公司产品缺陷,恩菲特公司对此负责。版权声明所有恩菲特公司出售的软件产品或随同硬件产品出售的软件和文件,其版杈属恩菲特公司所有,恩菲特公司保留软件产品和文件方面的所有版权。用户对产品的购买并不表示用户在版权方面的任何许未经恩菲特公司书面许可的任何复制和出售均是被禁止的成都恩菲特科拈冇限公司HTTP:www.enpht.comTel:028-851482738528FAX:028-85148287107第7页成都恩菲特科長有限公司EPH31580安全标志符号符号说明符号说明贴在产品上的标志符号表示仪器在操作前必须表示使用者必须遵循产品手保证相应的接线端接地册中相应的警告或注意内容良好,以免电击而引起以免造成人身伤害或设备损设备损坏或人身伤害。坏交流直流表示相应的操作危险。△操作员应严格按规定操高压危险。警告作,否则可能导致人身危险表示相应的操作危险操作员应严格按规定操凸⊥机外壳楼地通常与注意,否则可能寻受慢备设备的金属外壳相连接。损坏或永久性数据丢失HTTP:ww.enphtcomTEL:028-851482738528FAX:028-85148287107第8页成都恩菲特科長有限公司EPH31580敬在操作,维护及修理设备的整个过程中要严格遵守以下安全事项违反这些安全规程或任何本手册中警告和注意事项规定的操作导致的设备损坏或人身伤害,恩菲特公司不对此类事故承担责任●对第一类安全设备(具有俣护地接线端子的设各),必须在产品的主电源输入端或供电电源电缆提供一个可靠的安全地连接对于模块式设备,为确保模块安全接地,应将模块前面板上的紧固螺钉旋紧,以保证模块的紧固面板与机箱保护地可靠接通●仪器不应接触易燃易爆气体或在有易燃易爆气体的环境下操作●为了避免火灾,应使用具有相同电压和电流的保险溶丝。不能使用修理过的保险熔丝或短接保险盒●操作人员不应打开机盖。这只能由经过培训的专业技术人员进行。打开机盖是危险的,因为设备中可能存在危险电压。甚至在设备断电以后,高压也可能存在。为了避免人身伤害,应由经过培训的专业技术人员来操作。●不要操作危险设备或在危险的条件下操作设备。如果任何削弱安全性或可能导致安全保护设施失效的情况存在(包括物理损坏,潮湿或别的原因),应立即拔除电源线,直到由专业技术人员确认后方可操作●不要单独维修或调整仪器,以免发生危险时可得到帮助和救治HTTP:www.enpht.comTel:028-851482738528FAX:028-85148287107第9页成都恩菲特科長有限公司EPH31580不能更换或更改产品中的元器件,除非有明确的认可和授权。因为这将带来其它危险。如仪器出了故障,应将其送到恩菲特公司指定的维修点进行维修,从而保证仪器的各项功能文献版本吏新历史所有版本和手册更新及发行时间都列举在下面。手册的初始版本是Ver1.00。不论何时更新手册,版本号都在尾数加1。当更新涉及到较为重要的内容时,版本号中间的数加1,当更新涉及到核心内容时,版本号第一位数加1。更新的内容通过手册发行,包括修改的内容及对手册新增加的内容。新版本均包括了对旧版本更改的内容。每个新版本或更新后版夲都有一页标注该文献的更改情况Ⅴrl.0l..,,,∴,,.,2005.05HTTP:/ww.enphtcomTEL:028-85148273/8528FAX:028-85148287107第10页
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PCI Specification 3.0_PCI 3.0 规范
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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