matlab的CT图像重建代码

能够读取遥感影像，并利用Moravec和fostner算子提取特征点，内附影像

基于FPGA的SPWM的程序基于FPGA的SPWM的程序基于FPGA的SPWM的程序基于FPGA的SPWM的程序基于FPGA的SPWM的程序基于FPGA的SPWM的程序

无线信道建模的讲解，我们学校老师自己总结的，内附matlab程序

Vivado约束指导手册输入端口到输出端口路径在从输入端口直接到输出端口的路径上,数据:不需要在器件内部锁存(atch),直接从输入端口到输出端口。他们通常被称为ln-to-out数据路径端口时钟可以是虚拟时钟也可以是设计时钟路径举例图3-1描述了上面所有的路径,在此例图中,设计时钟CLKo可被用作端口时钟,这样既可以约束D|N延时也可以约束DOUT延时FPGA DEVICEBoardDeviceInternal Delay REGAData Path DelayREGB Internal DelayBoardDINi DOUT Device○A4InpOutputDelayBUFGPort ClockCLKOPort clockIn-2-out Data PathFigure 3-1: Path Example时钟路径部分每一个时钟路径由三个部分组成:源时钟路径数据路径目标时钟路径源时钟路径源时钟路径是由源时钟从它的源点(典型的是输入端口)到发送时序单元的时钟引脚之间的路径。对于从输入端口起始的时序路径来说,就不存在源时钟路径数据路径对内部电路,数据路径是发送时序单元和捕捉时序单元之间的路径发送时序单元的有效时钟管脚称为路径起始点捕捉时序单元的数据输入管脚称为路径结束点对于输入端口路径,数据路径起始于输入端口。输入端口是路径的起始点对于输出端口路径,数据路径结朿语输岀端口。输岀端口是路径的结束点。目标时钟路径目标时钟路径是由目标时钟从其源点(典型的是输入端口)到捕捉时序单元的时钟管脚之间的路径。对于结束于输出端口的时序路径,就没有目标时钟路径图3-2显示了3段典型的时序路径REGAData PathREGBEndpointSource Clock PathStartpointDestination Clock PathFigure 3-2: Typical Timing PathSetup和Hold分析vⅳ ado ide分析时序并且在时序路径终点时候报告时序裕量。时序裕量是指在时序路径终点数据要求时间和抵达时间的差异。如果裕量为正,从时序的角度考虑此路径是有效的。Setup检查为了计算数据所需的 setup时间,时序引擎:1.决定源时钟和目的时钟之间的普通周期。如果没有被发现,为分析考虑多达1000个时钟周期。2.检查覆盖普通周期上的起始点和终点所有上升和下降沿。3.在任何两个有效 active沿之间的最小正差值dela。这个deta被称为 setup分析的时序路径要求Setup路径要求示例假象2个寄存器之间的一条路径,这些寄存器由其相应时钟上升沿触发。这条路径有效的时钟沿只有上升沿。时钟定义如下:.clko周期6nsck1周期4nsCommon periodclko launch edgesSetup(1)Setup(2)clk1 capture edgesOns 2ns 4nss 8n5 10ns 12nsFigure 3-3: Setup Path Requirement Example图33显示有2个单独的源和目的时钟沿有资格受到 setup分析: setup(1和 setup(2):源时钟发送沿时间:0ns+1*T(ck0)=6ns目的时钟抓取沿时间:0ns+2*(ck1)=8nsSetup Path Requirement=抓取沿时间-发送沿时间=2ns在计算路径要求时候,需要考虑2个重要的点:1.时钟沿是理想的,那就是说,时钟树插入延迟不在考虑之内2.默认时钟在0时间点是 phase-aligned,除非他们的波形定义引进了 phase-shit。异步时钟相位关系未知。时序引擎在分析其间路径时候会考虑默认值。关于异步时钟的更多内容看下部分Setup分析数据要求时间Setup分析数据要求时间是指为了让目的单元能安全的采样数据,数据必须在这个时间点之前稳定。这个值基于:目的时钟采样沿时间.目地时钟延时源时钟和目的时钟的不确定性目的单元 setup时间Setup分析的数据抵达时间Setup分析的数据抵达时间,是指由源时钟发送的数据在路径终点的稳定时候所需要的时间。它的值基于:源时钟发送沿时间源时钟延时数据路径延时数据路径延时包括所有从起点到终点的单元(cel)和线(ne延时。在时序报告中, Vivado将 setup时序考虑为数据路径的一部分。相应的,数据到达和要求时间的公式为:Data Required Time (setup)= destination clock capture edge time+destination clock path delayclock uncertaintyData Arrival Time(setup)= source clock launch edge timesource clock path delay+ datapath delaysetup timeSetup裕量是指要求时间和实际抵达时间的差值:Slack (setup)= Data Required Time -Data Arrival Time在输入数据引脚寄存器上 Setup裕量为负值,说明寄存器有可能锁存到未知的值跳转到错误状态Hod检查Hod裕量的计算与 setup裕量计算直接相关。当 setup分析证明了在最悲观的情况下数据可以被安全捕捉,hold分析确保了:同样的数据不可能被前面目地时钟沿错误的抓取下一个源时钟沿发送的数据不能被用来分析 setup的目的数据沿抓取因此,为了找到hold分析的时序路径,时序引擎考虑了所有为 setup分析的源和目的时钟沿结合的可能。对每一种可能的组合,时序引擎:检查发送沿和减去一个目的时钟周期的抓取沿之间的差值.检查了加上一个源时钟周期的发送沿和抓取沿之间的差值.只保留时间差值最大的发送沿和抓取沿hold路径要求示例采用page33中 setup路径要求示例中的时钟。对于 setup分析那仅有2个可能的时钟沿组合:Setup Path Requirement (S1)=1*T(clk1)-0*T(clk0)= 4nsSetup Path Requirement (S2)=2*T(clk1)-1*T(clk0)=2ns那么相应的hod要求如下:For setup s1:Hold path Requirement (Hla)-(1*T(clk1)-1*T(clk1))-0*T(clko)=onsHold Path Requirement (Hlb)=1*T(clkl)-(0*T(clk0)+I*T(clko))=-2nsFor setup $2:Hold Path Requirement (H2a)=(2*T(clk1)-1*T(clk1))-1*T(clko)2nsHold path Requirement(H2b)=2*T(clk1)-(1*T(clk0)+1*T(clk0))=-4ns从上面可以看出最大的要求时间是Ons,这正好与源时钟和目的时钟第一次上升沿相吻合。Hold路径要求示例,page36显示了 setup检查沿和他们相关的hold检查。cIko launch edgesHla S1 H1b/H2a522bclk1 capture edgesOns 2ns 4ns 6ns 8ns 10ns 12nsFigure 3-4: Hold Path Requirement Example此例中,最终的hod要求时间不是来源于最紧的 setup要求。这是因为所有可能的 setup沿都会被考虑在内,是为了找到最又挑战性的hod要求。正如在 setup分析中,数据要求时间和数据抵达时间是基于以下条件计算的:源时钟发送沿时间.目的时钟抓取沿时间源和目的时钟延时时钟不确定性数据延时.目的寄存器hod时间Data Required Time (hold)= destination clock capture edge timedestination clock path delayclock uncertaintyData Arrival Time (hold)= source clock launch edge timesource clock path delaydatapath delayhold timeHod裕量是要求时间和抵达时间的差值Slack (hold)= Data Arrival Time Data Required Time正的时序裕量意味着即使在最悲观的情况下数据也不会被错误的时钟沿抓取。而负的hold裕量说明抓取的数据错误,而且寄存器可能进入不稳定状态。矫正( recovery和移除( removal分析矫正和移除时序检查与 setup和hold检查相似,区别就是它们应用于异步数据管脚例如set或者clear o对于异步复位的寄存器.矫正时间是异步 reset信号为了锁定新数据已经切换到它的无效状态之后,到下一个有效时钟沿之间的最小时间。移除时间是在异步复位信号安全切换到其无效状态之前,到第一个有效时钟沿之后的最小时间。下面的等式描述了这两种分析的sack是如何计算的Recovery check下面的等式描述了下面如何计算:Data Required Time (recovery ) =destination clock edge start time+ destination clock path delayclock uncertaintyData Arrival Time (recovery )= source clock edge start timesource clock path delaydatapath delayrecovery timeSlack (recovery)= Data Required Time Data Arrival TimeRemoval checkData Required Time (removal)= destination clock edge start timedestination clock path delayclock uncertaintyData Arrival Time (removal)= source clock edge start timesource clock path delay+ datapath delayremoval timeSlack (removal)= Data Arrival Time -Data Required Time正如 setup和hold检査,一个负的 recovery裕量和 remova裕量说明寄存器可能进入亚稳态,并且将未知的电子层带入设计中。定义时钟时钟数字设计中,时钟提供了从寄存器到寄存器之间可靠的传输数据的时间参考。 Vivado ide时序引擎用时钟特征来:计算时钟路径要求以裕量计算的方式报告设计时序裕量更多信息,参考时序分析这章为了得到最精确的最大的时序路径覆盖,时钟必须合理的定义。可以用下面的特征定义时钟:源时钟是指定义在时钟驱动引脚或者时钟树跟端口的时钟时钟沿可以由周期和波形特性的组合描述周期是ns级的,与描述的波形的时间周期相匹配.时钟波形是在时钟周期里,在数ns内时钟上升沿和下降沿绝对时间的列表列表必须包含偶数个值。第一个值一般与第一个上升沿吻合,除非另外指定,默认的时钟占空比是50%相位是ns。如图4-1所示,ck0周期10ns,占空比50%,相位0ns。Ck1周期8ns,占空比75%,相位2ns。CIkO: period 10, waveform =10 5]CIk1: period =8, waveform=2850%50%ClaOns5ns10ns15ns25%75%clkbOns 2ns8ns 10ns16nsFigure 4-1: Clock Waveforms Example传播【 propagated clock)时钟周期和波形特征体现了时钟的理想特征。当时钟进入FPGA器件并且经过时钟树传播时候,时钟沿会有延时而且会随着噪声和硬件特性而改变。这些特点被称为时钟网络延时( latency)和时钟不确定{ uncertainty)时钟不确定性包含下面内容:clock jitterphase error任何额外指定的不确定Vivado会默认的将时钟作为传播时钟,这意味着,这是非理想的时钟。这么做是为了提供包含时钟树插入延时和不确定性的裕量的值。特定硬件资源

圣诞节祝福网页，只需要在最下部对话框里改为你需要的名字即可，你可以上传到自己的网站、转发给朋友等。

该EXCEL表格可用于辅助带通滤波器设计。用户输入带通滤波器性能指标，表格快速给出低通原型滤波器的元件参数以及带通滤波器的归一化耦合系数、输入群时延、外部Q值等

求解非线性问题时 非线性volterra滤波的特性明显优于线性滤波器

使用CC2591作为CC2530的功放, CC2591 PAThe absolute maximum ratings and operating conditions listed in the CC2530 datasheet [1]and the CC2591 datasheet [4] must be followed at all times. Stress exceeding one or more ofthese limiting values may cause permanent damage to any of the devicesNote that these characteristics are only valid when using the recommended register settingspresented in Section 4.6 and in Chapter 8, and the CC2530 - EM reference designOperating Frequency240524835MHzOperating Supply Voltage2036VOperating Temperature-40CTC=25C, VDD=3.0V, f=2440 MHz if nothing else is stated. All parameters are measuredon the CC2530-Cc2591EM reference design [11] with a 50 Q2 loadReceive CurrentWait for sync, -90 dBm input levelWait for sync, -50 dBm input level24mATXPOWER OXE5166mATXPOWER OXD5149mATXPOWER OXC5138mATXPOWER OXB5127mATransmit currentTXPOWER OXA5115ATXPOWER = 0X95100mATXPOWER = 0X8594ATXPOWE=0×75mATXPOWE=0×6579APower Down Current PM2UAISTRUMENTSPage 3 of 19SWRA308ATC=25C, Vdd=3.0V, f= 2440 MHz if nothing else is stated. All parameters are measuredon the CC2530-CC2591 EM reference design with a 50 Q2 loadReceive Sensitivity HGM 1 %PER, IEEE 802. 15.4[6] requires -85 dBm-988dBmReceive Sensitivity LGM1 PER, IEEE 802. 15.4 [6] requires -85 dBm-90.4dBmSaturationlEEE 802.15. 4 [6] requires-20 dBm10dBmWanted signal 3 db above the sensitivity levelIEEE 802.15.4 modulated interferer at ieee 802.15.4 channelsInterferer Rejection+5 MHz from wanted signal, IEEE 802. 15. 4 [6] requires 0 dBdB+10 MHz from wanted signal, IEEE 802. 15. 4 [6] requires 30 dB49dB+20 MHz from wanted signal wanted signal at- 82d BmdBdue to in the external lna and the offset in cc2530 the rssi readouts from cc2530CC2591 is different from rssi offset values for a standalone cc2530 design the offsetvalues are shown in table 4.4High Gain Mode79LoW Gain mode67Real rssi Register value-Rssl offsetISTRUMENTSPage 4 of 19SWRA308ATc=25C, Vdd=3.0V, f=2440 MHz if nothing else is stated All parameters are measuredon the CC2530-CC2591 EM reference design with a 50 Q2 load Radiated measurements aredone with the kit antennaRadiated Emissionwith TXPOWer Oxe5Conducted 2. RF (FCC restricted band)-462|dBmConducted 3. RF(FCC restricted band46.5 dBmComplies withFCC 15.247. SeeChapter 7 for moredetails about regulatoryRadiated 2.RF(FCC restricted band)42.2dBmrequirements andcomplianceIEEE 802.15.4[6]requires max.35%%Measured as defined by IEEE 802.15. 4 6TXPOWER OxE5. f= EEE 802.15. 4 channels13TXPOWER= OXD5. f= EEE 802.15.4 channelsTXPOWER= OXC5 f= EEE 802.15.4 channelsMax error∨ ectorTXPOWER OxB5 f= IEEE 802.15. 4 channelsMagnitude(EVM)TXPOWER OxA5. f= IEEE 802.15.4 channelsTXPOWER 0X95. f= IEEE 802. 15.4 channels643333%%%%%%%TXPOWER= 0x85. f= iEEE 802. 15.4 channelsTXPOWER =0x75 f= IEEE 802. 15.4 channels%TXPOWER= 065. f= iEEE 802. 15.4 channelsThe RF output power of the CC2530- CC2591 EM is controlled by the 7-bit value in theCC2530 TXPOWER register. Table 4.6 shows the typical output power and currentconsumption for the recommended power settings The results are given for Tc= 25 C, Vdd3.0V and f= 2440 MHz, and are measured on the cC2530-CC2591 EM reference designwith a 50 Q2 load. For recommendations for the remaining CC2530 registers, see Chapter 8 oruse the settings given by SmartRF StudioOXE520166OxD519149OxC18138OxB517127OxA5161150x95141000x8513940X75860x651079Note that the recommended power settings given in Table 4.6 are a subset of all the possibleTXPOWER register settings. However, using other settings than those recommended mightINSTRUMENTSPage 5 of 19SWRA308Aresult in suboptimal performance in areas like current consumption, EVM, and spuriousemissionTc=25C, Vdd=3.0V, f=2440 MHz if nothing else is stated All parameters are measuredon the CC2530-CC2591EM reference design with a 50 32 load2221-2V201918171611121314151617181920212223242526251510OxE5OxC5OxA50X850x65540-30-20-1001020304050607080ISTRUMENTSPage 6 of 19SWRA308A98Avg 3.6VAva 3vAvg 2V110111213141516171819202122232425261023.6V-1062V-110-40-30-20-100102030405060708070604020-Wanted signal at:-82 dBm10ISTRUMENTSPage 7 of 19SWRA308ACC2530-CC2591EM High Gain ModeC C2530-CC2591EM Low Gain Mode- CC2530EM40000-100110100908070-60-50-40-30-20-100The IEEE standard 802.15. 4 [8] requires the transmitted spectral power to be less than thelimits specified in table 4.7If-fc>3.5 MHz-20 dB-30 dBmThe results below are given for Tc=25 C, Vdd=3.0V and f= 2440 MHz, and are measuredon the CC2530-CC259 1EM reference design with a 50 Q loadIEEE absoluteChannel 182432.52435243752442524452447.5ISTRUMENTSPage 8 of 19SWRA308AOnly a few external components are required for the CC2530-CC2591 reference design. Atypical application circuit is shown below in Figure 5.1. Note that the application circuit figuredoes not show how the board layout should be done. The board layout will greatly influencethe RF performance of the CC2530-CC2591EM. TI provides a compact CC2530CC2591 EM reference design that it is highly recommended to follow. The layout, stack-upand schematic for the CC2591 need to be copied exactly to obtain good performance. Notethat the reference design also includes bill of materials with manufacturers and part numbersL102 L10=TI INF inductorVDD13cc2530LA 1RF PANTCC2591 RF NFNPA EN(P1 1)i工工I NA FNP:1HGM ENPO 7)T:1Proper power supply decoupling must be used for optimum performance. In Figure 5.1, onlythe decoupling components for the CC2591 are shown. This is because, in addition todecoupling, the parallel capacitors C11, C101, and C131 together with, L101, L102, TL11TL101 and TL131 also work as RF loads. These therefore ensure the optimal performancefrom the CC2591. C161 decouples the AvDD blAs power.The placement and size of the decoupling components, the power supply filtering and thePCB transmission lines are very important to achieve the best performance Details about theimportance of copying the CC2530-CC2591EM reference design exactly and potentialconsequences of changes are explained in chapter 6The RF input/output of CC2530 is high impedance and differential. The CC2591 includes abalun and a matching network in addition to the PA, LNa and RF switches which makes theinterface to the CC2530 seamless. Only a few components between the CC2530 andCC2591 necessary for RF matching For situation with extreme mismatch(VSWR 6: 1 till 12: 1out-of-band as shown in Figure 6.2) it is recommended to include all the components asshown in Figure 5.1ISTRUMENTSPage 9 of 19SWRA308ANote that the PCB transmission lines that connect the two devices also are part of the RFmatching. It is therefore important to copy the distance between the devices, the transmissionlines and the stack-up of the PCB according to the reference design to ensure optimumperformanceThe network between the CC2591 and the antenna(L111, C112, C111 C113 and L112matches the CC2591 to a 50 2 load and provides filtering to pass regulatory demands. C111also works as a dc-blockR151 is a bias resistor the bias resistor is used to set an accurate bias current for internaluse in the cc2591The TI reference design contains two antenna options. As default, the Sma connector isconnected to the output of CC2591 through a 0 Q2 resistor. This resistor can be soldered offand rotated 90 clockwise in order to connect to the PCB antenna, which is a planar invertedF antenna(PIFA). Note that all testing and characterization has been done using the SMAconnector. The PCB antenna has only been functionally tested by establishing a link betweentwo EMs. Please refer to the antenna selection guide [6] and the Inverted F antenna designnote [7 for further details on the antenna solutionsISTRUMENTSPage 10 of 19SWRA308A

【实例简介】本资源中含有WCDMA仿真器的所有Matlab源代码，用于对在特定多径衰落环境下的WCDMA基站和移动设备的行为建模，具有较好的研究价值。

代码主要是基于stm32开发，包括两路ws2812b初始化代码，以及呼吸灯、跑马灯、彩虹灯等灯效程序，均是用pwm+dma的方式发送数据，不占用内存，本程序已用在项目中，可稳定运行。