基于STM32F4的小波变换移植（含小波分解与重构）

关于LDPC码编码和BP译码算法的matlab仿真！

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利用FPGA实现PCI配置空间的读写,参考博客http://blog.csdn.net/li171049/article/details/17655065

【实例简介】第1章 绪论 1. 1 引言 1. 2 扩频通信的基本原理 1. 2. 1 理想通信系统的带宽和S／N的互换关系 1. 2. 2 潜在抗干扰理论 1. 3 扩频通信中的基本参数 1. 4 本书的结构 参考文献 第2章 伪噪声序列 2. 1 引言 2. 2 伪噪声序列的性质及其产生 2. 2. 1 伪噪声序列的性质 2. 2. 2 伪噪声序列的相关性 2. 2. 3 伪噪声序列的部分相关 2. 3 m序列 2. 3. 1 m序列的性质 2. 3. 2 m序列相关函数的波形及功率谱 2. 3. 3 产生指定延迟的m序列及m序列的保密性研究 2. 3. 4 m序列的构造 2. 4 Gold序列及其他伪噪声码序列 2. 4. 1 Gold序列 2. 4. 2 其他伪噪声序列 参考文献 第3章 锁相环原理 3. 1 引言 3. 2 锁相环基本理论 3. 2. 1 一些基本公式 3. 2. 2 环路等效噪声带宽 3. 2. 3 数字锁相环的基本理论 参考文献 第4章 数字下变频器 4. 1 引言 4. 2 扩频通信中ADC参数的选择 4. 2. 1 ADC量化效应 4. 2. 2 数的表示法及其在量化中的影响 4. 2. 3 量化bit数的性能分析 4. 2. 4 在DDC中ADC的选择原则 4. 3 DDC的有效实现结构 4. 3. 1 数字混频器原理 4. 3. 2 同相 I 和正交 Q 的DDC实现结构 4. 4 DDC的多速率采样处理 4. 4. 1 整数M倍抽取 4. 4. 2 CIC滤波器 4. 5 采用CORDIC算法实现DDC 4. 5. 1 CORDIC运算器原理 4. 5. 2 CORDIC的VLSI结构 参考文献 第5章 直接数字频率合成器 5. 1 引言 5. 2 DDFS原理及其性能分析 5. 2. 1 直接数字频率合成器的工作原理 5. 2. 2 DDFS的杂散来源及其分布特性 5. 2. 3 改善DDFS杂散输出频谱的几种方法 5. 2. 4 DDFS的VLSI结构 5. 3 基于Galois域的数字控制振荡器 NCO 5. 3. 1 数字控制振荡器的数学原理 5. 3. 2 Galois域NCO的VLSI结构 参考文献 第6章 数字抑制载波跟踪环 6. 1 引言 6. 2 几种经典的载波跟踪环 6. 2. 1 抑制载波跟踪环的结构形式 6. 2. 2 松尾环的QPSK解调 6. 2. 3 16QAM解调环 6. 2. 4 通用载波恢复环 6. 3 数字Costas环的设计 6. 3. 1 数字Costas环的功能部件及参数设计 6. 3. 2 数字Costas环的VLSI结构 参考文献 第7章 扩频码序列的捕获 7. 1 引言 7. 2 统计随机信号检测理论的简单回顾 7. 2. 1 Bayes和Neyman Pearon假设检验 7. 2. 2 在加性高斯白噪声下对无衰落信号的非相干接收 7. 2. 3 吸收式Mark. v链和锁定检测理论 7. 3 几种典型的PN码捕获算法 7. 3. 1 相干扩频通信的PN码捕获算法 7. 3. 2 非相干扩频通信的PN码并行捕获算法 7. 3. 3 减少剩余码相位偏移效应的PN码捕获算法 7. 4 数字非相干混合并行捕获的VLSI结构 7. 4. 1 非相干混合并行捕获算法 7. 4. 2 非相干混合并行捕获算法映射至VLSI结构 7. 5 PN码捕获系统的自适应门限算法 7. 5. 1 单个数据样本的门限计算 7. 5. 2 基于窗口计数器的自适应门限算法 7. 5. 3 利用瞬时标定功率的自适应门限算法 参考文献 第8章 数字延迟锁定跟踪环 8. 1 引言 8. 2 DLL基本原理 8. 2. 1 全时间非相干DLL跟踪 8. 2. 2 单△型抖动环 TDL 跟踪 8. 3 关于PN码跟踪环性能的采样和量化效应分析 8. 3. 1 非等量采样 8. 3. 2 码跟踪环 8. 3. 3 环路分析 8. 4 抗多径效应的PN码跟踪算法 8. 4. 1 算法的系统描述 8. 4. 2 优化滤波器的加权 8. 5 数字非相干双△△DLL跟踪算法及VLSI结构 8. 5. 1 非相干双△DLL跟踪算法描述 8. 5. 2 环路参数设计及部分单元部件的VLSI结构 8. 5. 3 数字式非相干双△DLL的VLSI结构 8. 6 窄相关DLL原理及性能 8. 6. 1 窄相关DLL原理 8. 6. 2 窄相关DLL的统计特性分析 8. 6. 3 多径误差分析

Matlab代码：在小波变换后用近似系数的峰值获取该帧的基音频率

为了提高图像加密的效率和安全性， 采用态函数线性组合法构造了一种离散分数余弦变换函数， 利用其良好的正交性能及具有分数阶参数和周期参数的特点， 提出了一种基于离散分数余弦变换的图像加密新方法 该加密算法采用了图像分块( 图元) 的方法 将图像分成大小不同的图元， 使用离散分数余弦变换对每个图元分别进行行变换和列变换， 从而完成对图像的加密 实验结果分析表明， 该算法的加密效果 效率和抗穷举攻击能力是令人满意的

自己训练的分类器导入进行视频行人检测 代码亲测可行，算法需要再完善 提高实时性

Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents

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