MCP2515驱动-STM32-keil project

使用VS2013创建的工程，使用前需要安装并配置DirectShow环境。DirectShow实现视频的实时显示并抓图保存到本地。可以设置图像参数和视频格式。

本次Web应用开发环境:Eclipse+Mysql5.1+tomcat7.0; struts2+hibernate3+spring3导入项目后，右键项目Build Path-----Configure Build Path，把Libraries中的相关组件路径改成自己电脑的即可运行。用户分为管理员和普通用户，管理员可以对图书增删改查操作，用户则可以查找书籍，加入购物车，查看购物车，清空购物车，结算购物车。内含说明文档帮助配置，系统界面精简，程序结构明朗，代码易懂，适合初学者进行参考学习。下载了不会用请留言，看到必回。

hysplit是NOAA研发的一款进行气流反演的一款软件，通过气象数据进行分析大气输送通道。

Java学习笔记(必看经典)

【实例简介】matlab圆拟合非常好的程序 实际验证无误 效果非常不错

基于小波去噪，里面含有硬阈值去噪，软阈值去噪，半软阈值去噪等，已编译成功 MATLAB程序

常用经典OFDM同步算法的MATLAB程序，完整工程可直接运行

一种基于模糊算法的移动机器人路径规划策略． 利用超声波传感器对环境进行探测， 得到关于障碍物和目标的信息． 运用模糊推理将障碍位置信息与目标位置信息模糊化，建立模糊规则并解模糊最终使机器人可以很好的避障，从而实现了移动机器人的路径规划。第4期陈卫东:基于模糊算法的移动机器人路径规划按照同样的方法,可以建立起多种条件下的控制规则的合成隶属度结果规则.类似于这样的控制规则可归纳总结为很多条.在模糊控制规则的制定上采用基于控制器行为特性的方NB NSPS PBNBSPS PBA0.7式,将动作分为若干基本行为,复杂的行为可由几个简0.303X)嬷单行为按次序构成,可简化模糊控制规则的确定,并可10-5减少模糊控制规则的数目,避开被控对象的特性建模cmis-10-510 cm/s(a)左轮加速度b)右轮加速度3.4模糊推理图8左右轮合成隶属度函数模糊推理是模糊控制器的核心,它具有模拟人的3.5解模糊基于模糊概念的推理能力,该推理过程是基于模糊逻通过模糊推理得到的结果是一个模糊集合.但在辑中的蕴含关系及推理规则来进行的由模糊规则推实际模糊控制中,必须要有一个确定值才能控制或驱理出输岀量的隶属度根据 Mamdani模糊推理方法求取动执行机构.将模糊推理结果转化为精确值的过程称模糊关系矩阵0为解模糊.所以,解模糊的作用是将模糊集合映射为为了说明模糊推理控制器的工作过程,这里以机个确定的点.也就是把上面推理合成得到的左右轮加器人在FD=105cm;ID=117cm;RD=40cm;θ=45deg;υ速度模糊集合转化为一个精确值来控制机器人的运=3.5cm/s的状态为例来说明推理决策的过程.査询数动解模糊方法的选择与隶属度函数形状的选择、推理据库中的规则,此状态下的模糊规则为表格中的第5、方法的选择相关. MATLAB提供5种解模糊方法:面积6、11和12.由模糊规则的推理与合成(取极小,取极大)重心法、面积等分法、平均最大隶属度法、最大隶属度得到输出的隶属度如下取小法和最大隶属度取大法.本文仿真采用的重心第五个规则推理结果法.这种方法也称为质心法或面积中心法,是所有解模糊化方法中最为合理、最流行和引人关注的方法.该方NB NS 1Z PS PBNB NS 1ZPSPB法的数学表达式是0.3031p1(a)d(a1)10 cm/s2左轮加速度2)ALaI(a)左轮加速度b)右轮加速度图4规则5推理的左右轮合成隶属度函数第六规则推理结果:ar uR(ar)d(a,)右轮加速度=(3)NB NS IZ PS PBNB NSPS PB式中,表示输出模糊子集所有元素的隶属度值在连续0.20.2论域上的代数积分,而加速度的取值是表示其左右两0m/s2-10-5cn边的面积为相等.该方法计算复杂,但它包含了输出模(a)左轮加速度(b)右轮加速度图5规则6推理的左右轮合成隶属度函数糊子集所有元素的信息,也较精确.采用重心法将模糊第十一规则推理结果量转换成清晰量,再经过线性尺度变换为实际输入给直流电机的控制量控制移动机器人的移动NB NS 1Z PS PBNB NS IZ PS PB0.74仿真实验及结果分析为了验证本文提出的模糊控制方法的可行性,在10-5105cm/s210-5cnMatlab中利用 Simulink建立系统仿真模型,对控制规则(a)左轮加速度(b)右轮加速度图6规则11推理的左右轮合成隶属度函数进行了仿真,假设移动机器人的行驶速度为0.6m/s,使第十二规则推理结果:用 Fuzzy logic工具箱软件对模糊算法进行了仿真.在仿n真过程中,起点和终点的位置可以任意设置,障碍物的NB NS IZ PS PBPS大小、形状和位置也可以任意设置,这样就可以在任意环境下检验算法的正确性和可靠性0.20.2图9为当起点为(0,0),目标点为(9,9),在障碍物100cm/s2-10-5cmls存在时模糊算法和势场法的路径规划仿真.由图我们(a)左轮加速度(b)右轮加速度图7规则12推理的左右轮合成隶属度函数可以看出,模糊算法比势场法规划的路径更优.其工作4电子学报011年代价更小,行走的路径也更短由于速度的控制,比文5结论献[12]中只对转向角进行控制节省大量时间移动机器人由于传感器的限制以及周围环境的不移动机器人路径规划仿真确定性,很难预先对机器人的移动路径进行规划.本文目标点釆用了的模糊控制算法对移动机器人进行控制.这种8算法对移动机器人的运行环境几乎没有什么限制,它能在情况很复杂的未知环境里运行.对障碍物的形状及其个数也没有什么约束.并可避开传统算法中存在障碍物的对移动机器人的定位精度敏感,对环境信息依赖性强等缺点.并且通过对速度的控制使机器人比以前只2模糊算法路径dd对转角控制进行路径规划节省时间,具有很强的时效性.从实验中的移动轨迹可以看出,移动机器人的行为0起始点势场法路径表现出很好的一致性、连续性和稳定性参考文献10x/m图9模糊算法和势场法的仿真对比图[1]李磊,叶涛,谭民,等.移动机器人技术研究现状与未来在相同的环境下用A算法和模糊算法也进行了J].机器人,2002,24(5):475-480仿真对比,仿真路径图如图10.应用两种算法获得的最Li Lei, Ye Tao, Tan Ming. Present state and future development优路径如图所示.其中,A*算法计算量较大,并且Aof mobile robot technology research [J. Robot. 2002, 24(5)算法只能在环境信息已知的情况下找到路径而不适合475-480.(in Chinese)部分环境信息已知的情况,而且很不适合动态环境的2 Pradhan, DR Parhi, A K Panda. Potential feld method to路径规划.模糊算法显然比A算法规划的路径更优,navigate several mobile robots[ J. Applied Intelligence, 2006(25):321-333并且能够实现移动机器人的实时避障3]郝宗波,洪炳熔.未知环境下基于传感器的移动机器人路移动机器人路径规划仿真径规划[J].电子学报,2006,34(5):953-956目标点Hao Zong-bo, Hong Bing-rong Sensor-based path planning for8mobile robot in unknown environment[J. Acta ElectronicaSinica, 2006, 34(5): 953-956(in Chinese)64]周兰凤,洪炳熔.用基于知识的遗传算法实现移动机器人障碍物路径规划[J].电子学报,2006,34(5):911-914Zhou Lan-feng; Hong Bing-rong. a knowledge based geneticalgorithm for path planning of a mobile robot[ J. Acta Elec2模糊算法路径tronic Sinica, 2006, 34 (5): 911-914(in Chinese0[5]高庆吉,雷亚莉,胡丹丹,等.基于自适应感知复位算法的起始点A*算法路径移动机器人定位[J.电子学报,2007,35(11):2166-217110Gao Qing-ji, Lei Ya-li, Hu Dan-dan. A robot localizationr/m图10模糊算法和A*算法的仿真对比图method based on adaptive sensor resetting algorithm[ J].Acta对比实验表明,模糊算法不但优于人工势场法,也Electronica Sinica, 2007, 35(11): 2166-2171.(in Chinese)优于A算法模糊算法大大优化移动机器人的路径规6TLLe,C-JWu. Fuzzy motion planning of mobile robots in划,是一种很智能的路径规划方法.模糊算法仿真成功unknown environments[J]. Journal of Intelligent and RoboticSystems,2003,37(2):177-191(下转第980页)证明使用模糊控制进行路径规划时对移动机器人的运行环境几乎没有什么限制,它能在未知环境里运行.对作者简介障碍物的形状及其个数也没有什么约東.从仿真实验陈卫东男,1972年生于吉林长春,教授,主要研究方向为机器中的移动轨迹可以看出,移动机器人的行为表现出比人控制,智能算法及其应用,图像处理等较好的一致性、连续性和稳定性.采用模糊控制算法避E-mail:wdchen@ysu.edu.cn开了传统算法中存在的对移动机器人的定位精度敏朱奇光男,1978年生于浙江宁波,讲师,博士研究生,主要研究感、对环境的信息依赖性强等缺点方向为机器人控制,智能算法及其应用第4期陈卫东:基于模糊算法的移动机器人路径规划

帮助你学习数据结构，使你熟练掌握数据结构

PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510