直序列扩频通信系统Simulink仿真

GS算法的MATLAB，用MATLAB编写而成，需要的可以下

opencv 车辆检测 车辆识别 训练样本 cascade HOG HAAR LBP纯手工抠图 正样本

//********************************************************************#include "ps2.h"//********************************************************************#define clr_ps2_clk() (ps2_clk = 0)#define set_ps2_clk() (ps2_clk = 1)#define clr_ps2_data() (ps2_data = 0)#define set_ps2_data() (ps

应用MFC使用内存双缓冲实现实时曲线无闪烁显示，选中曲线可进行缩放

RPCA 源码 matlab yi Ma Robustpca

【实例简介】GPS时间转换程序，MATLAB版本。 gps2cal 将GPS周和周内秒转换到公历时间 gps2cal1 由公历日期和GPS周内秒计算公历时间 cal2gps 将公历GPS时间转换到GPS周和周内秒 mjd2cal 将简化儒略日转换到公历时间 cal2mjd 将公历时间转换到简化儒略日 jd2cal 从儒略日计算公历时间 cal2jd 将公历时间转换到儒略日 cal2wd 借助MJD，由公历年月日推算星期几，按照格里高利十三世的历法改革去掉1582年10月5日至14日 cal2wd1 由公历年月日推算星期几，按照英国人的做法去掉1752年9月3日至13日 cal2wd2 不借助MJD，由公历年月日推算星期几，去掉1582年10月5日至14日

该软件实现了AES-128加密方式的16进制字符加密，且能通过密码，密文进行解密。内含MFC源代码，可以进行二次开发。

大家可以直接将数据套进去就行了,但愿对你的多组数据求解有帮助。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

用matlab实现道路分割，包含了分割检测等多种算法 ，有效地实现了道路分割