关于语音识别的matlab程序

用matlab编写的表白代码，可自行更换文字、名字，欢迎使用~

matlab最快最强的核密度估计代码，容易上手

正则化粒子滤波算法用matlab程序实现，滤波跟踪比较

ADC, CRC, LED, SYSTICK, TIM, USART, KEY, 读芯片ID

很全面的TD-LTE的MATLAB仿真程序

极化合成孔径雷达Pauli分解源码，供初学者使用，较为基础。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

MFC实现聊天及文件传输的socket编程

人生第一个代码，和媳妇儿搞到深夜，支持下哈。需要修改文件的读取路径和储存路径。建议在arcgis里运行，在其他编译平台可能会出错，因为arcpy这个包不属于通用的那种python包。

摘要：针对光伏电池输出特性具有强烈的非线性，根据太阳能电池的直流物理模型，利用 MATLAB 建立了太阳能光伏阵列通用的仿真模型。利用此模型，模拟任意环境、太阳辐射强度、电池板参数、电池板串并联方式下的光伏阵列I-V 特性。模型内部参数经过优化，较好地反应了电池实际特性。模型带有最大功率点跟踪功能，能很好地实现光伏发电系统最佳工作点的跟踪。