STM32F407VET 基于DDS 用内置DAC实现实现多种波形输出，频率可调：范围1HZ-5MHZ

该协议是PCIe3.0协议完整版，介绍了PCIe的组成部分、工作原理有助于软件、硬件开发人员了解和应用PCIe

【实例简介】经过PCA处理后的MIMO雷达波束形成matlab代码

【实例简介】

【实例简介】本软件是学习模拟退火的很好的软件，里面还有很多examples，本人觉得十分珍贵，拿出来分享一下，对于参加数学建模的学弟分肯定有帮助，呵呵。。

很好的无人机飞控源码，无人机爱好者的福音

【实例简介】dsp2812步进电机控制实验程序，适用于新手学习，已调试

基于unity3d的联网斗地主服务端+客户端源码，实现了注册登录斗地主等功能

自己做的齿轮范成模拟系统，设置各项参数后，点确定就可生成范成轮廓，还有手动模式，可以一步步看到整个范成过程，自带国标模数第一和第二系列数据库，同时可计算出齿轮的其他参数。可以保存图片。做的比较辛苦，所以分要的多点，但是我觉的很值。

微信支付企业付款到个人，包括付款 以及 查询 参考文章http://blog.csdn.net/fengshizty/article/details/53204566

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group