28335芯片中文资料
28335的中文翻译资料，很好，很全面，几乎把英文版的意思都表达到了lEXASINSTRUMENTS寄存器校准多通道缓冲串行端口模块增强型控制器局域网模块和串行通信接口模块串行外设接口模块内部集成电路外部接器件支持器件和开发支持工具命名规则文档支持社区资源电气规范最大绝对额定值建议的运行条件电气特性流耗减少流耗流耗图散热设计考虑在没有针对的信号缓冲的情况下,仿真器连接时序参数符号安排定时参数的通用注释测试负载电路器件时钟表时钟要求和特性电源排序电源管理和监控电路解决方案通用输入输出输出时序输入时序针对输入信号的采样窗口宽度低功耗模式唤陧时序增强型控制外设增强型脉宽调制器时序触发区输入时序高分辨率时序增强型捕捉时序增强型正交编码器脉冲时序转换开始时序外部中断时序电气特性和时序串行外设接口模块主模式时序受控模式时序外部接口时序同步模式异步模式信号与致外部接口读取时序外部接口写入时序版权内容EXASINSTRUMENTS带有一个外部等待状态的外部接口读取准备就绪时序带有一个外部等待状态的外部接口写入准备就绪时序和定时片载模数转挨器加电控制位时序定义顺序采样模式(单通道)同步采样模式(双通道)详细说明多通道缓冲串行端口模块发送和接收时序作为主控或者受控时序闪存定时器件和器件之间的迁移到的修订历史记录到修订历史记录散热和机械数据内容权lEXASINSTRUMENTS图片列表引脚蒲型四方扁平封装(顶视图)焊球(左上象限)(底视图)焊球右上象限)(底视图焊球(左下象限)(底视图焊球(右下象限)(底视图)焊球塑料(左上象限)(底视图)焊球塑料(右上象限)(底视图)焊球塑料(左下象限)(底视图)焊球塑料(右上象限)(底视图)功能方框图内存映射内存映射内存映射外部和中断源外部中断使用块的中断复用时钟和复位域和块方框图使用一个外部振荡器使用一个外部振荡器使用内部振荡器实全装置模块功能方框图定时器定时器屮断信号和输出信号时基计数器同步方案子模块显示关键内部信号互连功能方框图功能方框图模块的方框图带有内部基准的引脚连接带有外部基准的引脚连接模块方框图和接口电路图内存映射内存吹射串行通信接口模块方框图模块方框图(受控模式外设模块接口方框图使用采样窗口的限定外部接口方框图典型的位数据总线连接典型的位数据总线连接的器件命名法示例典型运行电流与频率间的关系(典型运行功率与频率间的关系(版权图片列表EXASINSTRUMENTS在没有针对的信号缓冲的情况下,仿真器连接测试负载电路时钟时序加电复位热复位写入寄存器所产生的效果的示例通用输出时序采样模式通用输入时序进入和退出定时进入和退出时序图使用的唤醒特性或者时序外部中断时序主控模式外部时序(时钟相位)主控模式外部时序(时钟相位)受控模式夕部时序(时钟相位受控模式外部时序(时钟相位)和之间的关系示例读取访问示例写入访问使用同步访问读取的样本使用异步访问读取的样本使用同步访问写入使用异步访问写入外部接口保持波形时序要求加电控制位时序模拟输入阻抗模型顺序采样模式(单通道)时序同步采样模式时序接收时序发送时序作为主控或者受控时的时序:作为主控或者受控时的时序作为主控或者受控时的时序:作为主控或者受控时的时序图片列表权lEXASINSTRUMENTS图表列表碩件特性硬件特性信号说明中闪存扇区的地址中闪存扇区的地址中闪存扇区的地址处理安全代码付置等待状态引导模式选择外设引导加载引脚外设帧寄存器外设帧寄存器外设帧客存器外设帧寄存器器件仿真寄存器外设中断配置和控制奇存器外部中断寄存器,时钟,安全装置,和低功率模式寄存器设置分频选项可能的配置模式低功率模式定时器,,配置和控制寄存器控制和状态寄存器(屮的默认配置)控制和状态寄存器(在中重新映射的配置可由访问)控制和状态奇存器控制和状态寄存器寄存器寄存器汇总收发器寄存器映射寄存器寄存器寄存器寄存器寄存器寄存器复用器外设选择矩阵复用器外设选择矩阵复用器外设选择矩阵配置和控制寄存器映射外设选择指南时电源引脚的流耗为电源引脚的流耗不同外设的典型流耗(在上时)计时和命名规则(器件)版权图表列表EXASINSTRUMENTS计时和命名规则(器件)输入时钟频率时序要求被启用时序要求被禁用开关特性(旁通或者被禁用)电源管哩和监控电路解决方案序要求通用输出开关特性通用输入时序要求模式时序要求模式开关特性模式定时要求模式开关特性模式时序要求模式开关特性时序要求开关特性可编程控制枚障区输入定时要求在时,高分辨率特性增强型捕捉时序要求开关特性增强型正交编码器脉冲时序要求开关特性外部转换开始开关特性外部中断时序要求外部屮断开关特性时序主控模式外部时序(吋钟相位)主控模式外部时序(时钟相位)受控模式外部时序(时钟相位)受空模式外部时序(时钟相位中配置的参数和脉冲持续时间之间的关系时钟配置对于外部存储器接口读取时序要求外部内存接口读取开关特性外部存储器接口写入开关特性外部接口读取开关特性(读取准备就绪,个等待状态)外部接口读取时序要求(读取就绪,个等待状态同步时序要求(读取准各就绪,个等待状态)异步时序要求(读取准各就绪,个等待状态外部接口写入开关特性(写入准备就绪,个等待状态)同步时序要求(写入准各就绪,个等待状态异步时序要求(写入准各就绪,个等待状态)时序要求时序要求电气特性(在推荐的运行条件下)加电延迟不同配置的典型电流消耗(在上)图表列表权lEXASINSTRUMENTS顺序采样模式时序同步采样模式时序时序时要求开关特性作为主控或者受控定时要求作为主控或者受控开关特性主控或者受控时的定时要求作为主控或者受控开关特性作为主控或者受控定时要求作为主控或者受控开关特性作为主控或者受控定时要求作为主控或者受控时的开关侍性对于和温度材料的闪存耐受度闪存对于温度材料的耐受度上的闪存参数:闪存访问时序闪存数据保持持续时间不同频率上所需最小的闪存等待状态散热模型引脚结果散热模型引脚结果散热模型焊球结果散热模型焊球结果版权图表列表TEXASINSTRUMENTS数字信号控制器查询样品特性高性能静态技术增强型控制外设高达周期时间)多达个脉宽调制输出内核,设计高达个支持微边界定位分辨率高性能位的高分辨率脉宽调制器输出单精度浮点单元()(只在高达个事件捕捉输入上提供)多达两个正交编码器接口和双介质方问控制运算高达个位定时器(个以及个)哈佛总线架构高达位定时器快速中断响应和处理个以及个统一存储器编程模型三个位定时器高效代码(使用和汇编语言)串行端口外设通道处理器(用多达个控制器局域网模块和多达模块位或位外部接口高达个模块(可配置为)超过地址范围个模块片载存储器一个内部集成电路总线位模数转换器个通道闪存,转换率通道输入复用器闪存两个采样保持单一同步转换闪存,内部或者外部基准次性可编程多达个具有输入滤波功能可单独编程的多路复用引导通用输入输出引脚支持软件引导模式(通过边界扫描支持和并高级仿真特性标准数学表分析和断点功能时钟和系统控制借助硬件的实时调试支持动态锁相环开发支持包括比率变化片载振荡器编译器汇编语言连接器安全装置定时器模块到引脚可以连接到八个外部内核中断其中的一个数字电机控制和数字电源软件库可支持仝部个外设中断的外设中断扩展块位安全密钥锁保护闪存模块防止固件逆向工程标准标准测试端口和边界扫面架构A版权
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PCI Specification 3.0_PCI 3.0 规范
PCI 3.0 规范,英文原版。PCI Local Bus Specification Revision 3.0PCI LOCAL BUS SPECIFICATION, REV.3.0ContentsPREFACESPECIFICATION.……13INCORPORATION OF ENGINEERING CHANGE NOTICES (ECNS)1查音音鲁垂音音13DOCUMENT CONVENTIONS.………14l. INTRODUCTION…151.1. SPECIFICATION CONTENTS······151.2. MOTIVATION……151.3. PCI LOCAL BUS APPLICATIONS1. 4. PCI LOCAL BUS OVERVIEW171.5. PCI LOCAL BUS FEATURES AND BENEFITS……181. 6. ADMINISTRATION…………………202. SIGNAL DEFINITION m...mn.. 212.1 SIGNAL TYPE DEFINITION222.2. PIN FUNCTIONAL GROUPS..…………222.2.1. System Pins……,…,…,,…,…232.2.2. Address and data pins242.2.3. Interface Control Pins........................252.2.4. Arbitration Pins(Bus Masters Only)272.2.5. Error Reporting Pins....垂看d。普音看鲁D指音着音,。音音自。音音音。音自垂272.2.6. Interrupt Pins( Optional)……282.2.7. Additional signals312.2.8.64- Bit bus extension pins( Optiona)…,,……………………………332.2.9. TAG/Boundary scan Pins(Optional).......342. 10. System Management Bus Interface Pins(Optional)352. 3. SIDEBAND SIGNALS362. 4. CENTRAL RESOURCE FUNCTIONS.····:·····.·············363. BUS OPERATION373.1 BUS COMMANDS373.1. Command definition373. 1.2. Command Usage rules393.2. PCI PROTOCOL FUNDAMENTALS423.2.1. Basic Transfer Control····:············.················433.2.2. Addressing.............143.2.3. Byle lane and Byte enable usage……563.2.4. Bus Driving and Turnaround非音垂垂·非573.2.5. Transaction Ordering and posting….583. 2.6. Combining Merging, and Collapsing。。音垂。音62PCI LOCAL BUS SPECIFICATION, REV.3.03.3. BUS TRANSACTIONS……643.3.1. Read transaction……………653.3.2. Write transaction3.3.3. Transaction termination.………….673.4. ARBItRAtION音垂3.4.1. Arbitration Signaling protoco1..…………………893.4.2. Fast Back-to-Back Transactions. .........................................................93.4.3. Arbitration Parking………………………………………93.5 LATENCY953.5.1. Target Latency…….953.5.2. Master Data latency……….….…….,….….…..……..….,983.5.3. Memory Write Maximum Completion Time limit3.5.4. Arbitration Latency3.6. OTHER BUS OPERATIONS……·。垂,音着垂。着音D。。着。D音着音垂。音着D音非非音垂音非·非1103.6.1. Device selection…....…,103.6.2. Special cycle...........3.6.3. IDSEL Stepping…………,,…,…,,…,,…,,,,,………,…1133.6.4. Interrupt acknowledg3.7. ERROR FUNCTIONS春音·。音垂1153.7.. Parity ger1153.7.2. Parity Checking...........………,163.7.3. Address parity errors…...…,…163.7.4.Error Reporting…17173.7.5. Delayed Transactions and Data Parity Errors.......... 203.7.6. Error Recovery.............,213. 8. 64-BIT BUS EXTENSION1233.8.1. Determining bus Width during System initialization.…….…,1263.9.64- BIT ADDRESSING…..…………………………………………1273.10SPECIAL DESIGN CONSIDERATIONS.1304. ELECTRICAL SPECIFICATION.. m.m.9.1374.1. OVERVIEW…1374.1.1. Transition Road Map……1374.1.2. Dynamic vs Static Drive specificalion…1384.2. COMPONENT SPECIFICATION.……,………………,1…………………1394.2.1. 5V Signaling environment1404.2.2. 33V Signaling environment鲁鲁·垂垂1464.2.3. Timing specification1504.2.4.1determinate Inputs and metastable作,…………1554.2.5. Vendor provided specification..,..…,.…………….………17564.2.6. Pinout recommendation157PCI LOCAL BUS SPECIFICATION. REV.3.04.3. SYSTEM BOARD SPECIFICATION.………1584.3.1. Clock skew,…………………1584.3.2.R··1584.3.3. Pull-ups:····.················:·····…1614.3.4Power1634.3.5. System Timing Budget. ...........1644.3.6. Physical requirements............………674.3.7. Connector Pin assignments……/6844. ADD-IN CARD SPECIFICATION1714.4.1.Add- in Card Pin Assignment..,.,.,………………,1714.4.2. Power Requirements….,.,.,.,.,.,.,,.….,764.4.3. Physical requirements.........1785. MECHANICAL SPECIFICATION1815.1. OVERVIEW1812. ADD-IN CARD PHYSICAL DIMENSIONS AND TOLERANCES...........1825.3. CONNECTOR PHYSICAL DESCRIPTION…………………1954. CONNECTOR PHYSICAL REQUIREMENTS. ...............................2055. CONNECTOR PERFORMANCE SPECIFICATION……………,…2066. SYSTEM BOARD IMPLEMENTATION……………2076. CONFIGURATION SPACEb●看●鲁D鲁0e●2136. 1. CONFIGURATION SPACE ORGANIZATION音垂垂D·垂看垂…2136.2. CONFIGURATION SPACE FUNCTIONS .......................2166.2.1. Device ldentification鲁垂垂2166.2.2. Device Control鲁着鲁D垂2176.2.3. Device status2196. 2.4. Miscellaneous registers·······:········:···:·:··:·:······:··············4······:····2216.2.5. Base addresses……………………….22463. PCI EXPANSION ROMS2286.4. VITAL PRODUCT DATA.2296.5. DEVICE DRIVERS2296.6. SYSTEM RESET.…………………………2306.7. CAPABILITIES LIST2308. MESSAGE SIGNALED INTERRUPTS ...................................................................2316.8.1. MSI Capability Structure..............2326.8.2. MSl-X Capability and Table structures……………….……..2386.8.3. MSI and Msi-X Operation2467. 66 MHZ PCI SPECIFICATION2557. 1. INTRODUCTION2557.2. SCOPE7. 3. DEVICE IMPI TION CONSIDERATIONS7.3.1. Configuration space.......2557. 4. AGENT ARCHITECTURE256PCI LOCAL BUS SPECIFICATION, REV.3.07.5. PROTOCOL.……2567.5.1.66 MHZ ENABLE(M66EN) Pin definition.…………,………,,2567.52Latency..-..-.-2577.6. ELECTRICAL SPECIFICATION……………2577.6.. Overview·.·······.··2577.6.2. Transition roadmap to 66 MHz PCI··········.2577.6.3. Signaling Environment.......... 2587.6.4. Timing specification.……2597.6.5. Vendor provided specification. 26.57.6.6. Recommendations·.·························:············:······:········.:··········2657.7. SYSTEM BOARD SPECIFICATION.………,…,……………2667.7.1. Clock Uncertainty ......2667.7.2. Reset2677.7.3. Pullups..2677.7.4. Power..······.·.·::·····布鲁····音D鲁番。是。音垂看····非D∴2677.7.5. System Timing Budget7.7.6. Physical requirements2687.7.7. Connector Pin assi! nments…..,.,.,..,.,.,..,.,.,2697.8. ADD-IN CARD SPECIFICATIONS春音·。音垂2698. SYSTEM SUPPORT FOR SMBUSn2718. 1. SMBUS SYSTEM REQUIREMENTS2718.1.1. Power………278. 2. Physical and Logical sMBi27l8.1.3. Bus connectivit2728.1.4. Master and slave support....….….…..…..…..,2738.1.5. Addressing and Configuration2738.1.6.Ele2748.1.7. SMBus behavior on Pcl reset.........................2748.2.ADD- IN CARD SMBUS REQUIREMENTS…………2758.2.7Connection2758.2.2. Master and Slave Support...,.…..…….…,...….,2758.2.3. Addressing and Configuration……,…,…,……,…,…,…,….….…..….,2758. 2. 4. Power2758. 2.5. Electrical.········.····························275A. SPECIAL CYCLE MESSAGES●鲁●e鲁277A 1. MESSAGE ENCODINGS277A,2. USE OF SPECIFIC ENCODINGS ................................................277B. STATE MACHINES279B. 1. TARGET LOCK MACHINE·;.···.:..···:...···:··.·:····281B.2. MASTER SEQUENCER MACHINE283B 3. MASTER6PCI LOCAL BUS SPECIFICATION. REV.3.0C. OPERATING RULES289C 1. WHEN SIGNALS ARE STABLE..·····.:·.·.::···:·;289C.2. MASTER SIGNALS…音·。·看290C.3. TARGET SIGNALS…291C.4. DATA PHASES…292C.5. ARBITRATION.……………………………………292C.6. LATeNCY······:“·······293C.7. DEVICE SELECTION……………,……………………………293C 8. PARITY垂垂垂D·垂294D. CLASS CODESD 1. BASE CLASS OOH...w.w...296D 2. BASE CLASS OlH296D. 3. BASE CLASS O2H··297D 4. BASE CLASS O3H297D.5. BASE CLASS04H.………………………298D. 6. BASE CLASS OSH298D.7. BASE CLASS06H...………….…………………299D 8. BASE CLASS OZH,300D 9. BASE CLASS OSH.301D.10. BASE CLASS C9H.……………………………………………….301D.11. BASE CLASS OAH.…………………302D 12. BASE CLASS OBH302D. 13. BASE CLASS OCH303D.14. BASE CLASS ODH….…304D. 15. BASE CLASS OEH304D. 16. BASE CLASS OFH·····.····;····:·;:·······304D.17. BASE CLASS JOH.……………………………………………1305D, 18. BASE CLASS 11H305E. SYSTEM TRANSACTION ORDERINGE.I. PRODUCER- CONSUMER ORDERING MODEL308E. 2. SUMMARY OF PCI ORDERING REQUIREMENTS310E.3. ORDERING OF REQUESTS........................................311E.4. ORDERING OF DELAYED TRANSACTIONS…………312E.5. DELAYED TRANSACTIONS AND LOCK#.317E.6. ERROR CONDⅠ TIONS……318. EXCLUSIVE ACCESSES..m.msn0..319F.1. EXCLUSIVE ACCESSES ON PCIF 2. STARTING AN EXCLUSIVE ACCESS321F.3. CONTINUING AN EXCLUSIVE ACCESS323F 4. ACCESSING A LOCKED AGENT324F 5. COMPLETING AN EXCLUSIVE ACCESS325F. 6. COMPLETE BUS LOCK ......................................................................325IO SPACE ADDRESS DECODING FOR LEGACY DEVICES..9.... 327PCI LOCAL BUS SPECIFICATION, REV.3.0CAPABILITY IDS。,0329I. VITAL PRODUCT DATA331VPD FORMAT3I.2COMPATIBILITY……………………………334L.3. VPD DEFINITIONS3341.3.1. VPD Large and small resource Data Tags......·D垂看3341.3.2. VPD Example…3378PCI LOCAL BUS SPECIFICATION. REV.3.0FiquresFIGURE -I: PCI LOCAL BUS APPLICATIONS春DFIGURE 1-2: PCI SYSTEM BLOCK DIAGRAM17FIGURE2-1: PCI PIN LIST.…………..…………21figure 3-1: ADDRESS PHASE FORMATS OF CONFIGURATION TRANSACTIONS...... 48Figure 3-2: LAYOUT OF CONFIG ADDRESS REGISTER, ..............................................50Figure 3-3: HOST BRIDGE TRANSLATION FOR TYPE O CONFIGURATION TRANSACTIONSADDRESS PHASE51FIGURE3-4: CONFIGURATION READ…………156FIGURE3-5: BASIC READ OPERATION………………………65FIGURE 3-6: BASIC WRITE OPERATION66FIGure 3-7: MASTER INITIATED TERMINATION........................ 68FIGURE3-8: MASTER- ABORT TERMINATION…………69Figure 3-9: RETRY. ..........................................................................................................73FiGure 3-10: DISCONNECT WITH DATA. ........................74FiGure 3-11: MASTER COMPLETION TERMINATION:·:····:··.·4····.···…75FiGURE 3-12: DISCONNECT-1 WITHOUT DATA TERMINATION·····76Figure 3-13: DISCONNECT-2 WITHOUT DATA TERMINATION76FiGure 3-14: TARGET-ABORT…177figure 3-15: BASIC ARBITRATIONFIGuRE 3-16: ARBITRATION FOR BACK-TO-BACK ACCESS…94FiGurE 3-17: DEVSEL# AsSERTION·····:···.·:··110Figure 3-1 8: IDSEL STEPPING114FiGure 3-19: INTERRUPT ACKNOWLEDGE CYCLE. ...................................................114FIGURE3-20: PARITY OPERATION………116FIGuRE 3-21: 64-BIT READ REQUEST WITH 64-BIT TRANSFER125FIGURE 3-22: 64-BIT WRITE REQUEST WITH 32-BIT TRANSFER..........126FIGURE 3-23 64-BIT DUAL ADDRESS READ CYCLE129FIGURE 4-1: ADD-IN CARD CONNECTORS...........................138FIGURE4-2:V/ICURⅤ ES FOR5 V SIGNALING.…………………143FIGURE 4-3: MAXIMUM AC WAVEFORMS FOR 5V SiGnaling145FIGURE 4-4: V/I CURVES FOR 3.3V SIGNALING148FIGURE4-5:MAⅹ IMUM AC WAⅤ EFORMS FOR3.3ⅴ SIGNALING………150FIGURE 4-6: CLOCK WAVEFORMS151FIGURE 4-7: OUTPUT TIMING MEASUREMENT CONDITIONS.··4·:······.·154FIGURE4-8: INPUT TIMING MEASUREMENT CONDITIONS…………154FIGURE 4-9: SUGGESTED PINOUT FOR POFP PCI COMPONENT···“···:.···.····:·········157FIGURE4-10: CLOCK SKEW DIAGRAM………158FIGURE 4-1: RESET TIMING16lFIGURE4-12: MEASUREMENT OF TPROP,3.3 VOLT SIGNALING……………166FIGURE 5-1: PCI RAW ADD-IN CARD(3.3V, 32-BIT).183FIGURE 5-2: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 32-BIT)..........184FIGURE 5-3: PCI RAW VARIABLE HEIGHT SHORT ADD-IN CARD(3.3V, 64-BIT)....185FIGURE 5-4: PCI RAW LOW PROFILE ADD-IN CARD(3.3V, 32-BIT)..........186PCI LOCAL BUS SPECIFICATION, REV.3.0FIGURE5-5: PCI ADD-Ⅰ N CARD EDGE CONNECTOR BEⅤEL……187FIGURE56: PCI ADD-IN CARD ASSEMBLY(3.3V)……………………………88FIGURE 5-7: LOW PROFILE PCI ADD-IN CARD ASSEMBLY 3.3V)189FIGURE 5-8: PCI STANDARD BRACKET………190FIGuRE 5-9: PCI LOW PROFILE BRACKET191FIGURE 5-10: PCI STANDARD RETAINER···192FIGURE5-11: IO WINDOW HEIGHT∴………………193FIGURE 5-12: ADD-IN CARD INSTALLATION WITH LARGE IO CONNECTOR.......194FIGURE 5-13: 32-BIT CONNECTOR196FIGURE 5-14: 3.3V/32-BIT CONNECTOR LAYOUT RECOMMENDATION. ........................197FIGURE5-15:3.3V/64-BIT CONNECTOR198FIGURE 5-16: 3.3V/64-BIT CONNECTOR LAYOUT RECOMMENDATION 199FIGURE 5-17: 3.3V/32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES2(垂D·。垂,音着垂。着音D。。着。D音着音垂。音着音FIGURE 5-18: 3.3V/64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES….201FIGURE5-19: UNIVERSAL 32-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES………………………………202FIGURE 5-20: UNIVERSAL 64-BIT ADD-IN CARD EDGE CONNECTOR DIMENSIONS ANDTOLERANCES203FIGURE5-21:PCⅠADD- IN CARD EDGE CONNECTOR CONTACTS……204FIGURE5-22: CONNECTOR CONTACT DETAIL………………205FIGURE 5-23: PCI CONNECTOR LOCATION ON SYSTEM BOARD208FIGURE5-24:32- BIT PCI RISER CONNECTOR……209FIGURE 5-25: 32-BIT/3.3V PCI RISER CONNECTOR FOOTPRINT210FIGURE 5-26: 64-BIT/3.3V PCI RISER CONNECTOR211FIGuRE5-27:64-BI/3.3ⅴ PCI RISER CONNECTOR FOOTPRINT∴………212FIGURE 6-1: TYPE OOH CONFIGURATION SPACE HEADER215FIGURE 6-2: COMMAND REGISTER LAYOUT217FIGURE6-3: STATUS REGISTER LAYOUT……………………………219FIGURE 6-4: BIST REGISTER LAYOUT222FIGURE 6-5: BASE ADDRESS REGISTER FOR MEMORY........... 225FIGURE 6-6: BASE ADDRESS REGISTER FOR L/O225鲁着D音看FIGURE 6-7: EXPANSION ROM BASE ADDRESS REGISTER LAYOUT.....,..... 228FIGURE6-8: EXAMPLE CAPABILITIES LIST…….231FIGURE6-9: MSI CAPABILITY STRUCTURES…..……233FIGURE 6-10: MSI-X CAPABILITY STRUCTURE238FIGurE 6-11: MSI-X TABLE STRUCTURE翻音。音239FIGurE 6-12: MSI-X PBA STRUCTURE…239FIGURE 7-1: 33 MHZ PCI VS 66 MHZ PCI TIMING······:··················257FIGURE7-2:3.3 V CLOCK WAVEFORM.…………259FIGURE 7-3: OUTPUT TIMING MEASUREMENT CONDITIONS263FIGURE -4: INPUT TIMING MEASUREMENT CONDITIONS263FIGURE75:TvAL(MAX) RISING EDGE…………264FIGURE 7-6: TVAL(MAX) FALLING EDGE·265FIGURE77:TVAL(MIN) AND SLEW RATE……26510
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