QPSK调制解调过程的MATLAB仿真

本程序主要对SIRT算法进行Matlab实现，共包含三个m文件。运行时，首先执行GenerateSIRTSystemMatrix.m生成系统矩阵A。然后，每需要重建一副图像时运行一次SIRTOnce.m或SIRTOnceSTD.m。其中，SIRTOnce.m对应了固定步长的SIRT算法，SIRTOnceSTD.m为采用最速下降原理对迭代步长进行优化以后的SIRT算法，并采用FBP算法进行对比重建。

资源包含了上位机和下位机程序，利用modbus协议采集下位机的两个温度（其中一个温度由DS18B20模块测量，一个是写在51芯片的固定值），LCD显示温度，报警范围，通过键盘可以修改温度报警范围，报警状态由LED灯代替，上位机显示温度、报警范围等信息，同时可以由上位机修改相关参数，确保程序可以运行

大灰狼远程管理V8.96.zip

压缩感知各种重构算法经典论文合集 MP OMP SAMP SP CoSaMP ROMP StOMP IHT等以及RIP准则

Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents

压缩感知基础内容，包括陶哲轩在外面讲座的ppt和一些大牛对CS的见解。

AES的S盒可以用扩展的欧几里德和费马定理来写，这里我采用费马定理。要注意的是S盒的求逆过程是在加瓦罗域下进行的，所以里面的所有乘法、除法、加法、减法都是在加瓦罗域下进行。

电力系统继电保护 课程设计 论文有详细过程目录第一篇绪论第二篇原始资料分析…第三篇相关理论第四篇35KV线路相间短路的电流与残压…第五篇保护的配置与整定计算第六篇对全网保护的评价34第七篇结束语第八篇参考文献36第一篇绪论1.1设计题目35K单侧电源环网相间短路保护的配置与整定计算12设计任务1环网保护的配置与整定计算:针对本题,即保护1~8的配置与整定计算;2.单侧电源的单回线路保护的配置与整定计算:针对本题,即保护9的配置与整定计算;3.平行双回线路的配置与整定计算:针对木题,即保扩11~-14的配置与整定计算4.对全网保护进行评价:5绘制相关图纸6编写设计论文13设计综述通过对原始数据进行分析,结合所学知识以及查阅资料说的知识与技术,分别针对单侧电源单回线路、单侧电源平行双回线路和单侧电源环网发生相间短路故障时,进行了倮护的配置与整定计算,最终设计出一套完整的保护方案。第二篇原始资料分析2.1系统接线图如图2-1、图2t=05卩=1000kw35N单电源环网接线图(第3题cosc=0. 8NKL-10200568200/35BoKo四a「a2XSFL-8000/35=1500kwcs中=08■sL-250/35800MTi2XQF-25-2 T320Km35c0s中=8口2XSHL2000/35T62XQ252口QQT9t=05S-1600/35n=8bQGs=08卩=1500KM0so=082XQF-122ADkm102XSH31500352XSFL-15000/35SUMtL030Km卩=1500KwS200/350s中=08图2-12.2设备与线路的型号及参数采用标幺值进行计算,因为标幺值计算可以直观的判断结果的合理性,可以简化计算,运算方便,不用进行电压等级转换。这里采用采用标幺值的近似计算方法2.2.1基准值SB=100MWAUB1OKVUB=10. 5Kv, IB0=5.199%A,ZaUB10.51.1039B③*10.510035KV:Up-=37KY1001.560KAB13.69Q3B√337B157121B325040320.9375087661169xXI2]|[l3.25U0403209375H2○~T2T8325004D3202414B3X~八x040320.4141023G4EXAT9053308GX087661169X3250G60.533307873X1610TX15 Ti20876G图22.2.2发电机发电机型号本题代号CosφXGQF2-25-2G1G2G3G40.1160.80.4032QF2-12-12c5(G60.11120.7873计算公式xG=Xd*n一米COsq算例(QF2-25-2):X6=0.116*1000.80.1032252.2.3变压器变压器利号本题代号Uk%TSjL1-2000/35T71011126.53.25SFL1-8000/358.00.9375SjL1-1600/356.54.0625SFL1-31500/35T3T48.00.254SFL1-15000/35T5T68.015.00.5333J1-1250/35255.2计算公式:100算例(SJL1-2000/35):Xr1003.251002.2.4电抗器电抗器型号X1%NKL-10-200-66%0.2101.571计算公式XL=X1%水1*N算例:XL=6%5.499100.210.52.2.5线路线路名0BX10CD300.8766DE401.16900.40.58437FE1.023CG1.169CH(单回线)300.8766计算公式X*=X0米LB算例(Xp):XD=0.4求30*100=0.876637*372.3指定参数KA=0KK,=1.2relK=1第三篇相关理论31对电力系统继电保护的基木要求动作于跳闸的继电保扩,在技术上一般应满足四个基木要求,即选择性、速动性、灵敏性和可靠性;(1)选择性继电保护动作的选择性是指保护动作装置动作吋,仅将故障元件从屯力系统中切除,使停电范围尽量缩小,以保证系统中的无故障部分仍能继续安全运行。(2)速动性快速的切除故障可以提高电力系统并列运行的稳定性,减少用户在电压降低的情况下工作的时间,以及缩小故障元件的损坏程度。因此,在故障发生时,应力求保护装置能迅速动作切除故障。(3)灵敏性继电保护的灵敏性,是指对于其保扩范围内发生故障或者不正常运行状态的反应能力。满足灵敏性要求的保护裝置应该是在事先规定的保护范围内部故障时,不论短路点的位冒、短路的类型如何,以及短路点是否有过渡电阻都能敏锐感觉,正确反应。(4)可靠性保护装置的可靠性是指在该保护装置规定的保护范围内发生了它应该动作的故障时,它不应该拒绝动作,而在任何其他该保护不该动作的情况下,则不应该误动作。32运行方式电力系统的运行方式包括:最大运行方式,最小运行方式和主要运行方式最大运行方式是指(1)流过保护的短路电流为最大的运行方式:(2)根据系统最大负荷的需要,把系统中仝部的发电设备都投入运行的方式(3)在本设计中,系统中发电机和变压器全部投入,而且环网开环运行的运行方式;最小运行方式是指:(1)流过保护的短路电流最小的运行方式:(2)根据系统最小负荷的需要,投入与之相应的发电设备的运行方式(3)在本设计中,系统所带负荷最小,切除对短路电流影响最大的台发电机或变压器,而且环网闭环运行时的运行方式;主要运行方式是指:1)在一年之中,运行时间最长的运行方式;(2)根据系统负荷的需要,投入相应的发电设备的运行方式3)在本设计中,系统中的发电设备全部投入运行,而且环网闭环运行的运行方式3.3电流三段整定原则和校验原则电流Ⅰ段保护的整定原则及灵敏度校验原则(1)整定原则:按躲开本线路末端的最大短路电流来整定:2)校验原则:按最小运行方式下两厢短路吋的保护范围大亍被保护线路全长的15%来校验。按上述方法,若灵敏度不够,则采川电压电流联锁速断保护电流Ⅱ段保护的整定原则及灵敏度校验原则(1)整定原则:按躲开下一级各元件电流速断保护的最大动作值来整定(2)校验原则:按最小运行方式下,线路末端发生两相短路时有烂够的反应时间来校验,若按上述灵敏度不够,则首先考虑相继动作能否满足,若仍不满足则考虑与下一级线路电流Ⅱ段相配合,若仍不满足,则按灵敏度的要求进行反推,但必须满足选择性的要求:若仍不满足,这采用低电压启动的电流Ⅱ段保护电流∏段保扩的整定原则及灵敏度校验原则:1)整定原则:按躲开流过倮护安装处的最大负荷电流来整定。(2)校验原则:当作为本线路的主保护时,应采用最小运行方式下本线路末端两相短路时的电流进行校验;当作为相邻线路的后备保护吋,则应采用最小运行方式下相邻线路末端两相短路时的电流进行校验,按上述方法灵敏度不满足时,则采用低电压启动的过电流保护。34三段式电流速断保护的动作时限电流Ⅰ段为0s,电流Ⅱ段若与下一级线路的i段相配合,则为0.5s;电流Ⅱ段若与下一级线路的Ⅱ段相配合,则为1s电流Ⅲ段按吋限的阶梯原则来选择。35电流电压联锁速断保护瞬时电流速断保护具有很好的快速性,但当系统运行方式变化很大时,保护范围很小,甚至没有保护区。在不增加保护动作时限的条件下,可以增加一个低电压继电器构成电流电压联锁速断保护增长保护范围。由亍采用了电流和电压两个测量元件,在外部短路故障吋,只要冇个测量元件动作,保护就能保证选择性。动作电流是在正常运行方式下,保护范围末端三相短路故障时流过保护的短路电流。动作电压是在正常运行方式下,保护范围末端三项短路时,母线上的残余电压。36横联差幼电流方向保护平行双叫线往往用横差保护作为主保护的补充。樻联差动电流方向保护是反应平行双冋线电流不同前动作的保护。当1线电流I1与Ⅱ线电流I存在I1-Im>0关系时,判别I线路发生短路故障,Ⅰ线路断路器动作。否则Ⅱ线路断路器动作3.7电流平衡保护电流平衡保护是用电流平衡继电器来判別平行线路屮的故障线路。电流平衡保护是按比较平行双回线中电流的绝对值而动作的,同时还引入电压量进行制动3.8延时电流电压保护由于电流保护受系统运行方式变化影响很大,为了在不増加动作时限的前提卜,提高保护的灵敏性,可应采用电流电压保护。延时电流电压保护电压定值按保证测量元件范围末端故障吋冇足够的灵敏系数整定。电流定值按保护本线路木端故障有规定灵敏系数整定,还应与相邻线路保护测量元件定值配合。时间定值整定方法与阶段式电流保护相同第四篇35K∨线路相间短路的电流与残压41单侧电源单回线路41.1最大运行方式1电网接线图,(如图4-1)0A032040820403202414093515712177B32504032D2414GeR-9 i MLT05333078730.9375X1169H60533307X~X回回T6图4-12等效电网接线图,将电源电抗进行串并联计算,得Xd>:=0.1588,(如图42)15712177B3.25c图4-23.电流与残压计算(1)首端短路:(3)Kmax0.5781Xd∑+(XL)0.1588+(1571)3)(X1)=0.5781*1.571=09082

【实例简介】压缩感知理论能够有效地降低高分辨率雷达成像系统的数据率。该文通过对复基带雷达回波信号模型的稀疏性分析，提出了一种具有保相性的压缩感知距离压缩法。在此基础上建立了距离向采用压缩感知距离压缩算法，方位向采用传统的雷达成像算法处理的雷达2 维成像方案。通过对仿真和实测逆合成孔径雷达数据的成像处理验证了方案的有效性。

From within the MATLAB file browser double click on this file, it will install and configure the paths correctly