《汇编语言源代码大全》

该程序有详细的注释，易于读者理解与运用。

参照博客C# JSON和对象之间互相转换用Winform进行了JSON和对象之间转化的呈现，并用Socket来传输JSON。原文链接：http://www.cnblogs.com/HCCZX/p/5238556.html

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

这是北航数值分析大作业的全部三道题目的完整版源代码+算法分析，由本人在理学院本科期间完成。包括：1.QR分解法求矩阵特征向量2.幂法、反幂法求矩阵特征值3.最小二乘法进行函数曲面拟合希望大家不要直接照搬代码，因为每年的题目中具体数字可能会变。

《天线与电波传播》（宋铮） 电子课件，方便学习参考

很好的非线性调频信号的产生程序，根据不同的窗函数产生不同的信号

CRC4-ITU X4+X+1CRC5-EPC X4+X3+1CRC5-ITU X5+X4+X2+1CRC5-USB X5+X2+1CRC6-ITU X5+X2+1CRC7-MMC X7+X3+1CRC8 X8+X2+X+1CRC8-ITU X8+X2+X+1CRC8-ROCH X8+X2+X+1CRC8-MAXIM X8+X5+X4+1CRC16-IBM X16+X15+X2+1CRC16-MAXIM X16+X15+X2+1CRC16-USB X16+X15+X2+1CRC16-MODBUS X16+X15+X2+1CRC16-CCITT X16+X12+X5+

文件包含了OFDM发送端信号生成的MATLAB代码和相应的课程报告

深入浅出数字信号处理书籍PDF版本，入门学习信号处理很适合。

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