加速遗传算法

相关滤波代码，2015年的最新版本，可以运行，MATLAB版本，适合从事目标跟踪和计算机视觉的相关研究者下载学习，有助于提高对相关滤波的认识，代码运行的实时性非常好，可以说是目前实时性最好的一种跟踪算法

时频分析工具TFSAP6.3，可以用于matlab仿真信号处理，特别是非平稳信号的处理

Fanuc机床Focas开发包，包含完整的Focas函数功能讲解，其中有英文和日文的XML文档，以及中文汇总的Word文档和C#代码示例，方便大家学习。

猪场供料自动控制系统，由根据猪舍内单元塞链的启动条数自动控制下料电机的频率控制下料多少。

关于移动机器人路径规划的ppt，参考了大量文献，涵盖了几乎可以看到的所有成熟路径规划算法并且加入了很多作者本人的理解。希望对需要的朋友有所帮助。-on mobile robot path planning ppt reference to the vast body of literature, cover almost all can see the maturity path planning algorithm and to the many authors I understand. Hope to a friend in need of help.

基于QT 5做的usb插拔检测，我主用是用于检测usbkey的(通过 VID,PID)，其他设备应该也是可以的,测试过u盘，usb转串口线，usb key都能识别，

这是一个BP算法实验报告，是郑州大学的，大家可以参考下

dsp在线升级

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

本片是基于Matlab的Levenberg-Marquardt算法参考代码，通过代码，可以加快我们对LM算法求取目标参数的方法掌握，加深对非线性最小二乘法的理解