学生选课管理系统(数据库课程设计)
学生选课管理系统 数据库课程设计目录第一章系统规划1.1引言..b垂1.1.1编写目的.1.1.2项目背景1.2可行性研究的前提1.2.1目枋1.2.2要求1.2.3条件假定和限制1.2.4决定可行性的主要因素1.3技术可行性分析3.1技术的支持能力.11122333333.2技术的优势.1.3.3技术的难点1.4经济可行性分析1.4.1预期支出1.4.2预期收益1.5社会可行性分析333444441.5.1法律因素.1.5.2用户使用可行性.1.6意见结论第二章需求分析2.1系统需求垂鲁垂垂垂2.2功能需求2.3数据流图..2.3.1系统顶层图2.3.2数据流程图一层分解图2.3.3数据流程图二层分解图2.4数据字典.2.4.⊥数据流条目2.4.2数据处理132.4.3数据存储.14第三章概念设计...153.1实体之间的联系153.2ER图153.2.1局部E-R图第四章逻辑设计..11概念模型向关系模型的转换194.1.11:N联系的转化的关系模式4.1.2M:N联系的转化的关系模式194.2概念模型的优化04.2.1确定范式级別04.2.2实施规范化处理20第五章物理设计.5.1数据库的存储结构.,225.1.2数据库的表设计225.1.3数据的存放位置的设计245.1.4关系模式的存取方法245.1.5.数据库安仝性.21第六章实现、运行与维护.256.1实现,,,256.1.1数据库的实现.256.1.2视图的实现256.2人机界面设计,事b··垂···,,,,,,,,276.2.1用户登陆界面276.2.2学生选课管理界面.276.2.3教师管理界面.286.2.4管理员管理界面.6.3系统测试296.3.1用户脊陆测试296.3.2学生选课管理测试,,,,,,,296.3.3教师管理测试306.3.4管理员管理测试、4运行维护....,32总结33参考文献34学生选课管理系统第一章系统规趔第一章系统规划1.1引言1.1.1编写目的可行性研究的日的是川最小的代价在尽可能的短的时间内确定数据库系统是否可能开发、是否值得开发、是否可以开发(在该报告中主要是考査《学生选课管理系统》是否可能开发、是否值得开发、是否可以开发)。其实质是在较高层次上以较抽象方式进行的、简化的压缩的需求分析和概要设计过程。1.1.2项目背景开发软件名称:学生选课管理系统项目任务提出者:李军项目开发者:洪峰、陈梓明等用户:各大高校师生1.2可行性研究的前提1.2.1目标系统实现后,极大的方便对学生进行选课和选课后临时班级的安排管理,学生选课信息的管理。避免在安排课程信息的滞后,减少信息交流的烦琐过程及其带来的丌销。促进髙校教育的计算机信息化进程,提髙学校的工作效率。对于系统的本身而言,应该具有较高的实用性、安全性。能够极大的满足学生选课,以及学校对选课信息的管理学生选课管理系统第一章系统规趔1.2.2要求主要功能:教师和学生登陆系统的帐号和密码,初始都分别为教师和学号,登陆后密码可以修改。其屮教师的职位可以是管理员。管理员和非管理员的老师及学生对系统的操作具有不同的权限。管理员登陆系统,对学生选课情况进行管理,包括发布选课信息,对学生的选课情况进行查看。管理员还可以对授课老师的信息进行增加、删除、修改、查询。教师脊陆系统,能査看自己的个人信息,及所授课的班级的所有学生的本门课程的成绩信息,并能进行增加和修改。学生登陆系统,能进行选课,查看管理员发布的选课信息,自己的选课情况,本人的基本信息,以及课程的成绩。系统自动分巸学生选课后的临时班级。性能要求管理员发布的信息、学生选课的信息以及管理员和学生对系统操作的信息必须及时的反映在本系统上,且无差错输入要求:具有很好的容错性和兼容性输出要求:应迅速、准确、实吋完成期限:预计五个星期,即截止2011年12月30日。1.2.3条件假定和限制建议软件寿命:未知经费来源:自费硬件条件: Intel pentium4、lG内存同等性能及以上的硬件条件运行环境: WindowⅪP、 Tomcat5.5、JDK1.6数据库: Microsoft sQL server2005投入运行最迟时间:2012年1月5日学生选课管理系统第一章系统规趔1.2.4决定可行性的主要因素技术可行,现有技术可完全承担开发任务操作可行,软件能被操作人员快速接受绎济可行,为小型系统软件,支出较小。社会可行,使用软件全部为正版,且本软件在法律允许范围之内1.3技术可行性分析技术上的可行性分析要考虑现有技术条件能否顺利完成开发工作及将来要采用的硬件和软件技术能否满足用户提出的要求。1.3.1技术的支持能力木系统采用J2EE企业级开发方案,其中 MyEclipse8.5作为系统前台应用程序丌发工具,采用 SQL Server2005工具建立数据库,并通过JDBC使两者进行连接从而进行系统软件开发。此前,我们已使用相同技术开发过类似软件系统,具有一定开发经验。此外,从开发人员的水平考虑,本系统的软件开发人员,都具有较强软件开发能力,且之前开发都参加过类似软件系统的开发,经验卡富。3.2技术的优势、J2EE体系结构提供中间层集成框架用来满足无需人多费用而又需要高可用性、高可靠性以及可扩展性的应用的需求、开发效率、代码重用率高;、跨平台,编写次,随处运行;四、开发界面友好,智能。1.3.3技术的难点数据库设计和维护、系统负荷和安全问题学生选课管理系统第一章系统规趔1.4经济可行性分析1.4.1预期支出基础投资计算机10台:5000*10=5万人员工资:5000儿*2月*10人=10力官传费用:1万其他不可知支出:2万支出共计:18万本学生选课管理系统其它所需的硬件(计算机及相关硬件)和软件环境MyEclipse8.5+ Tomcat.5.5+JDK1.6+ SQL Server2005),市场上都容易购买到或从相关网站下载。其屮JDK1.5为开源免费软件。而 SQL server2005本软件采用的是学习版,也是免费的, MyEclipse8.5以前已经购得,开发成本较小。1.4.2预期收益预期发售价格:2万/套目标客户:全国各大高校预期发售量:40套/年预期收益:40米2=80万预期收益>预期支出,开发本系统能够为投资者带来较高的收益。1.5社会可行性分析1.5.1法律因素开发使用的所有软件都选用正版,其中JDK1.5为开源免费软件。而SQLserver2005木软件采用的是学习版,也是免费的学生选课管理系统第一章系统规趔1.5.2用户使用可行性本软件操作简单,界面友好,功能完备,有一定计算机基础的人员就能进行操作。6意见结论根据上述分析,技术、济、社会可行性都可行,可以立即进行开发。学生选课管理系统第二章需求分析第二章需求分析2.1系统需求用户的需求具体体现在选课信息和用户信息的提供、保存、更新和查询的方面。这就要求数据库的设计必须合理,使之能够充分满足各种信息的输入和输出,保证数据存储的可靠性,并且能够快速取出和存入。而前台显示部分,应具有人性化的界面,方便用户操作。因各个学校的实际情况不同,系统应该具有兼容性。例如:一些学校学生人数较多,同时登陆系统,系统承载的负荷就很大。系统需要同时处理很人的数据量,这时系统不会因此崩溃。此外,系统还应该具有较强的安全性,保证身份不同的用户,不能越权操作。非合法用户不能对数据进行操作2.2功能需求通过系统功能的分析,结合需求分析员在各大高校实地考查,调查的对象涵盖了,学校的教职工、在校师生。特别是对已经运行了与本系统同类产品的学校的师生使用选课管理系统心得体会进行了分析,总结出如下的需求信息(1)学生的需求:能进行选课,査看管理员发布的选课信息,自己的选课凊况,本人的基本信息,课程的成绩;()教师的需求:能查看自己的个人信息,及所授课的班级的所有学生的本门课程的成绩信息,并能进行增加和修改;〔3)管理员的需求:对学生选课情况进行管理,包括发布选课信息,对学生的选课情况进行査看。管理员还可以对授课老师的信息进行管理。
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Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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