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一个西电中期答辩的PPT，关于鲁棒水印设计。中期答辩其实就是相当于这段时间毕设进度的汇报工作，重要但不是太严格。

超分辨率图像处理，matlab源码，效果远远优于三次插值

用VC实现了小波变换，小波逆变换，低通滤波，高通滤波，阈值滤波，信噪比等功能，绝对能用

2015电赛 风力摆控制系统赛题解析及源代码开源 里面的风力摆开发分析很透彻！

php网络直播聊天室源码财经直播聊天室系统喊单直播间系统源码

本书是开关电源类的经典书籍，几乎所有搞电源的的人士都知道这书，但是现在书店基本不卖，是一本很好的书。

大学实训项目，用java实现银行管理系统简单的开户、挂失、存、取、贷款、转账等一系列操作(数据库是mysql，加载一下驱动就可以运行了)

全国土壤数据集，来源于联合国粮农组织（FAO）和维也纳国际应用系统研究所(IIASA)所构建的世界和谐土壤数据库(Harmonized World Soil Database )(HWSD),该数据库于2009年3月26日发布了1.1版本.该数据可为建模者提供模型输入参数,农业角度可用来研究生态农业分区,粮食安全和气候变化等。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group