试卷自动生成系统毕业论文.doc

非常好用的modbus主从站模拟器，可以直接解压使用，不需要安装，附带说明

本实例完成RTX与Windows进程通信，包含两个工程：1、Windows MFC 程序，创建共享内存，并可完成对共享内存的读写操作；2、RTX进程通过读共享内存完成通信。开发环境：MS VS2005。参考资料： RTX Help文档。推荐资料：博客http://wzhyblog.yo2.cn/articles/tag/rtx

基于arcgis10.0做dem和坡度分析图

PID调节直流电机转速c语言实现pid算法控制直流电机转速，转速led显示，可用按键调整转速。

网络ns2仿真实验分析(RED、丢包率、端到端延迟、吞吐量)附源码分组的端口号。(10) dst addr:目的地址,格式为 node port,其中node代表分组发送节点的id,pot表示发送分组的端口号。(11) seg num:分组的序列号。(12) okt id:分组的唯标识符。3n2与n3之间的RED队列的半均队列长度与当前队列长度随时间的变化如下图所示:torrent and ave"吧 e PED CueL旧300era已n15000ANA图2平均队列长度与当前队列长度随时问变化的曲线图4运行结果中显示CBR流量总共发包550,丢失16,丢包率为:0.029。丢包率随时间的变化如下图所示:packets of lost rate。045graph自04,03500自020.015图3丢包率随时间变化的关系图5CBR流量的吋延随时间的变化如下图所示:1u彐r10.14心01Q。0图4端到端时延随时间变化的关系图6.节点n2的平均吞吐量随时间的变化如下图所示100T图5节点n2的吞吐量随时间变化的关系头7.结果分析:从RED的图示中,可以看出队列的大小波动变化不是很大,在处理突发的包时冇一定的优势。从丟包率、时延和吞吐量的变化图中,可以看出当丟包率增加时,端到端之问的时延也在增加,而吞吐量则下降,丟包率、时延和吞吐量在表示网络性能的好坏时有一定的关系、相关代码1.络拓扑仿真脚木 simulator:tcl:#Create a simulator objectset ns [new Simulator]#Define different colors for data flows for NAM)Sns color 1 BlueSns color 2#Open the nam trace fileset nt lopen out. nam wSns namtrace-all Snfset nd [open out. tr wISns trace-all Snd#Define a finish procedureproc finish仆}{global ns nf ndSns flush-traceclose Snfclose sndexec nam out. namkit o#Create four nodesset no [Sns node]et n1 [Sns nodelset n2 [Sns nodeset n3 [ns node]#Create links between the nodesSns duplex-link Sn0 Sn2 2Mb 10ms DropTailSns duplex-link Sn1 Sn2 2Mb 10ms DropTailSns duplex- link Sn2 Sn3 1.7Mb 20ms RED#Set queue Size of link (n2-n3 to 100Sns queue-limit Sn2 Sn 3 100#Give node position(for NAm)Sns duplex-link-op SnO Sn2 orient right-downSns duplex-link-op Sn1 Sn2 orient right-upSns duplex-link-op $n2 Sn3 orient right#Monitor the queue for link(n2-n3 .( for NAM)Sns duplex-link-op Sn2 Sn 3 queuePos 0.5#Setup a TCP connectionset tcp new Agent/TCPISns attach-agent Sno Stcpset sink [new Agent/TCPSinkSns attach-agent sn3 SinkSns connect stcp SinkStcp set fid 1#Setup a FTP over TCP connectionset ftp [new Application/FTPlSftp attach-agent StcpSftp set type FTPfsetup a UdP connectionset udp [new Agent/UDP]Sns attach-agent Sn1 udpset null [new Agent/Nul]Sns attach-agent Sn3 SnullSns connect Udp SnullUdp set fid_ 2#Setup a CBr over UDP connectionset cbr [new application/Traffic/ CBRIScbr attach-agent UdpScbr set type CBrScbr set packet size 1000Scbr set rate 1mbScbr set random false#Schedule events for the cbr and ftp agentsSns at0.1 Scbr startSns at 1.0"Sftp start"Sns at 40.0"Sftp stop"Sns at 4.5"Scbr stop"#Detach tcp and sink agentsSns at 50 Sns detach-agent $no stcp; Sns detach-agent sn3 Sink"Sns at 50.0 finish#monitor n2 and n3 queueset redg [[sns link Sn2 Sn3] queueset traceq lopen redQueue tr wSredg trace curgSredg trace aveSredg attach Strace#Run the simulationns rur2.RED的数据处理脚本:SgreparedQueue. tr>averagetrStrep“Q" reqUeuetr> current tr(中 reqUeue tr为跟踪n2和n3队列产生的文件)然后使用 gnuplot工具使用 average tr和 current, tr绘制队列随时间变化的曲线3.丢包率数据awk处理脚本 graph rostRate,awvk#count the packet lost rate of cBri=0;vente=S2;from Node =$3toNode=s4:pitT$7srcAddr=$9dstAddr=$10gNum = $11if (fromNode ==1 & toNode ==2&& event==+i totalNum++timeArr[i=timesrate[i]= float)(drop Num/tif(fid==2&& event==d")dropNum++ENDprintf("#number of packet sent: %od, lost: %d"totalNum, dropNum)printf( #lost rate of packets: %f",dropNum/totalNumfor(j=0; j

Matlab 官方有关于HDL coder开发的详细技术文档， HDL Coder可以把Simulink模型、MATLAB代码和Stateflow框图生成位真、周期精确、可综合的Verilog和VHDL代码，很适合用于FPGA/ASCI的快速开发，里面还有大量的例程等等ContentsHDL Code generation from MATLaBMATLAB Algorithm DesignData Types and scope1-2Supported data TUsuppyted data type1-3Scope for variables1-3Operators1-4Arithmetic operate1-4Relational operators1-4ogical Operators1-5Control flow statements1-6Vector Function Limitations related to Control1-7PersistentⅤ ariables1-8Persistent Array variables1-10Complex data Type Support1-11Declaring complex signaIs1-11Conversion Between Complex and real signals1-12Support for vectors of Complex Numb1-12ystem Objects1-14Why use System objects?1-14Predefined System Object1-14User-Defined System ob1-14Limitations of HDL Code Generation for SystemObjects1-15System object Examples for HDL Code Generation.. 1-16Predefined System Objects Supported for HDL CodeGeneration1-17Load constants from a mat-file1-18Generate Code for User-Defined System Objects1-19How To Create a User-Defined System object1-1User-Defined System object Example1-19Map Matrices to ROM1-22Fixed-Point bitwise Functions1-231-23Bitwise Functions Supported for HDl Code Generation 1-23Fixed-Point Run-Time Library functions1-29Fixed-Point function limitations1-33Model State with Persistent variables and SysteObjects1-34Bit Shifting and bit rotation1-8Bit Slicing and Bit Concatenation1-41Guidelines for Efficient hdL code1-43MATLAB Design Requirements for HDL CodeGeneration1-44What is a matlab test bench?1-45MATLAB Test Bench Requirements and bestractices1-46MATLAB Test Bench requirements1-46MATLAB Test bench best practices1-46ContentsMATLAB Best Practices and Design Patterns forHDL Code generation2Model a counter for hdl code generation2-2MATLAB Counter2-2MATLAB Code for the counter2-3Best Practices in this Example2-4Model a state machine for HDL Code Generation2-5MATLAB State machinesMATLAB Code for the Mealy State MachineMATLAB Code for the moore state machine2-7Best practic2-9Generate hardware Instances For local functions2-10MATLAB Local functions2-10MATLAB Code for mlhdlc two counters. m2-10Implement RAM USing MATLAB Code2-13Implementation of RAM2-13Implement RAM Using a Persistent Array or Systemobject Properties2-13Implement RAM Using hdl. RAM2-14For-Loop best Practices for HDL Code generation2-16MATLAB Loops2-16Monotonically Increasing Loop Counters2-16Persistent Variables in Loops2-17Persistent Arrays in Loops2-17Fixed-Point Conversion3Floating-Point to Fixed-Point Conversion3-2Fixed-Point Type Conversion and Refinement3-16Working with Generated Fixed-Point Files3-26Specify Type Proposal Options3-33Log Data for Histogram3-37Automated Fixed-Point Conversion3-40License Requirements3-40Automated Fixed-Point Conversion Capabilities3-40Code Coverage3-42Proposing Data Types3-45Locking Proposed Data Types3-47Viewing functions3-47lew1ariables3-48Istogram ...3-54Function Replacements3-56Validating Types3-57g Numerics3-57Detecting Overflows3-57Custom plot functions3-59Visualize Differences Between Floating-Point and Fixed-Point results3-61Inspecting Data Using the Simulation Data Inspector 3-67What Is the Simulation Data Inspecto3-67Import Logged Data3-67Export Logged data3-67Group signals3-67Run options3-68Create Report3-68Comparison Options3-68Enabling Plotting Using the Simulation Data Inspector 3-68Save and Load simulation Data Inspector Sessions3-68Enable Plotting Using the Simulation Data Inspector 3-70From the UI3-70From the Command Line3-70Replacing Functions Using Lookup TableApproximations·3-72Replace a custom function with a lookup Table3-73From the UI3-73i ContentsFrom the Command line3-81Replace the exp Function with a Lookup Table3-84From the ui3-84From the Command line3-92Data Type Issues in Generated Code3-94Enable the highlight Option in a MaTLAB CoderProject3-94Enable the Highlight Option at the Command Line... 3-94Stowaway doubles3-94Stowaway singles3-94Expensive Fixed-Point operations3-94Code GenerationCreate and set Up Your Project4-2Create a New Project4-2Open an Existing ProjectAdd Files to the project4-4Primary Function Input Specification4-6When to Specify Input Properties4-6Why You must Specify Input Properties4-6Properties to Specify4-6Rules for Specifying Properties of Primary Inputs4-8Methods for Defining Properties of Primary Inputs4-8Basic hdl code generation with the workflowAdvisor4-10HDL Code Generation from System Objects4-14Generate Instantiable code for functions4-19How to generate Instantiable Code for Functions4-19Generate Code Inline for Specific Functions4-19Limitations for instantiable code generation forFunctions4-19Integrate Custom HDL Code Into MATLAB Design.. 4-21Define the hdl. Black Box System object4-21Use System object In MATLAB Design Function4-23Generate HDL Code4-23limitations for hdl. black box4-26Enable matLab function block generation4-27Requirements for MaTLAB Function Block Generation 4-27Enable matlab function block generation4-27Results of matlab function block generation4-27System Design with HDL Code Generation fromMATLAB and simulink4-28Generate Xilinx System Generator Black Box Block4-32Requirements for System Generator Black Box BlockGeneration4-32Enable System Generator black Box block GeResults of System Generator Black Box Bloc neration4-32Generation4-33Generate Xilinx System Generator for DsP black boxfrom MATLAB HDL Design4-34Generate HDL Code from MATLAB Code Using theCommand line interface4-40Specify the Clock Enable rate4-45Why specify the clock Enable rate?4-45How to Specify the clock Enable rate4-45Specify Test Bench Clock Enable Toggle rate4-47When to Specify Test Bench Clock Enable Toggle rate4-47How to Specify Test Bench Clock Enable Toggle rate4-47Generate an HDL Coding Standard report fromMATLAB4-49Using the hdl Workflow advisor4-49Using the Command Line4-51Generate an HDL Lint Tool script4-53How To generate an hdl lint Tool Script4-53ContentsGenerate a Board-Independent Ip core from MATLAB 4-55Generate a board-Independent Ip core4-55Requirements and Limitations for IP Core generation4-57Minimize clock enables4-58Using the GUi4-59Using the Command Line4-59Limitations4-59VerificationVerify Code with HDL Test Bench5-2Generate Test bench with file i/oWhen to Use file i/o In Test bench5-5How Test bench generation with file i/o works5-5Test Bench Data files5-5How to generate Test bench with file i/o5-6Limitations When Using File 1/0 In Test Bench5-6DeploymentGenerate Synthesis Scripts6-2Optimization7RAM Mapping7-2Map persistent Arrays and dsp. Delay to RAM7-3How To Enable RaM Mapping7-3RAM Mapping requirements for Persistent Arrays andSystem object PropertiesRAM Mapping Requirements for dsp. Delay Systemob7-6RAM Mapping Comparison for MATLAB Code7-8Pipelining7-9Port registers7-9Input and Output Pipeline registers7-9Variable pipelining7-9Register Inputs and Outputs7-10Insert Input and Output Pipeline registers7-11Distributed Pipelining7-12What is Distributed Pipelin7-12Benefits and Costs of Distributed pipelining7-12Selected Bibliograph7-12Pipeline matlab variables7-13Using the hdl Workflow Advisor7-13Using the Command Line Interface7-13Limitations of MatlAB Variable Pipelining7-13Optimize MatLAb loops7-15oop Streaming7-15Loop unrolling7-15How to Optimize maTLaB loops7-15Limitations for MaTLAB Loop Optimization7-16Constant Multiplier optimization7-17Specify constant multiplier optimization7-19Distributed Pipelining for Clock Speed Optimization7-20Map Matrices to Block RAMs to Reduce Area7-27Resource Sharing of Multipliers to Reduce Area7-32Loop streaming to Reduce Area7-41Contents

保证可运行，生成的APK包可运行的android系统的手机上具有详细的注释，非常适合android入门者和具有一定基础的开发者参考学习

基于ROS构建无人驾驶车辆环境感知系统，文档描述对于基于ros开发有较大的帮助

有程序和资料。17年华为杯数学建模D题，针对问题一，在静止背景条件下，提取运动前景目标轮廓，首先处理视频，生成单帧数据，针对不含纯背景帧的视频采用帧间差分法，对含背景帧的视频数据采用背景差分法。两种方法都可以准确提取静止背景下的前景目标轮毂，最后进行形态学的补充处理，达到预期的效果。针对问题二，分析动态背景每一帧之间都大面积的不同，因此使用帧差法的结果会出现大量的噪点。采取混合高斯模型(GMM)对动态的背景进行建模，采用一定帧数的图像来训练模型，从而实现实时更新的背景模型，过滤掉背景变化对目标提取的影响，可以准确提取前景目标。针对问题三，考虑摄像头抖动造成图像的变化，因此考虑首先去抖动，对

地震三维正演模拟并行计算程序，用的是粘弹性波动方程，在linux下运行，需要安装并行环境，比如mpich