非线性控制时滞系统迭代学习控制算法仿真

【实例简介】用于秉火系BH-MSD4805步进电机的测试，keil5编写，在main.c里给出了阅读代码的指导，本程序通过usart串口指令控制步进电机加减速、步数、最大速度，代码移植方便，程序已经过本人调试正常跑通。调试需要注意一些硬件问题：1、电机及驱动器最好配套，电流电压调节合适；2、通电后检查电机是否锁死；祝各位调试愉快！

vc6操作数据库，从数据库到listbox读写数据。自己的测试代码，保证能用。

arcengine进行的二次开发的经典案例，可以实现IDW，克里金插值，。适合C#初学者,以及从事ARCGIS二次开发的初学者。

matlab图像超分辨处理与重建的代码，基于matlab开发，界面操作的

个人收集的Python3.x+Pyqt5制作GUI界面的案例，可以参考其制作GUI界面，设计界面结构等。

matlab的视觉伺服工具箱 ,主要用在机器人控制上,

随着社会经济的发展和信息技术的高度发达，越来越多的企业和个人的购物方式和以前有了实质的改变，网上商店逐渐增多，交易的方式也从以前的网上发布，然后网下交易购买，发展到了直接通过网络进行在线支付，随着物流的发展，交易的物品也从以前的大件物品，发展到现在几乎所有商品都能在网上购买。因此，为了更方便顾客购物，就需要有一个功能比较完善的网上商城系统来实现这个平台。网上商城系统是解决实体商城各种问题的一种方法。因此该课题具有一定的意义和研究价值。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

这是关于数学建模的文档，有matlab 的源代码，用了阻滞增长模型和multhus模型，用于预测中国未来人口数变化

数学辞海（第二卷 Vol2）(全六卷) by 裘光明等 数学辞海编辑委员会.pdf