ALINX黑金Zynq7000开发平台配套教程
当我们拿刡开収板是否应该测试一下收刡癿开収板是否功能正常，以及各个接口工作是否工作正常。在出厂前我们已经在SD卡里存储了启劢程序和操作系统，所以开収板上电就能启劢幵可以用杢测试各个部分接口和电路癿工作是否正常。通过测试也使大家对我们开収板癿功能有一个大致癿认识。ALINXOALNX黑金2ynq7000开发平台配套教程序首先感谢大家购买黑金动力社区出品的zYNQ7000的开发板AX7010和AX7020!您对我们和我们产品的支持和信任给我们增添了永往直前的信心和勇气。赛灵思公司xinx)于2012年推出zynq7000SOC芯片解决方案,该方案将双核ARMCortex-A9和 FPGA Fabric集成在一颗芯片上,通过内部总线连接,ARM和FPGA之间的通信速度大大提高,从而提高芯片整体性能。但同时,ARM和FPGA两门之前独立的软硬件学科在一颗芯片上应用,大大提高了芯片入门门槛。黑金这两年一直在筹划推出Zynq7000S0C系列硬件开发平台,同时编著一套教程,循序渐进,由浅入深,旨在让学员很轻松的入门,体验最前沿的ARM+ FPGA SOC技术。本教程根据不同的侧重点分4部分:第一部分是基础篇,分别介绍开发板的上电捡测,硬件电路的介绍,zYNQ芯片的介绍,软件 Vivado的安装, Linux系统虚拟机的安装,PS和P接口技术的介绍和zYNQ开发流程的介绍。通过基础篇让大家对黑金开发板AX7010/A×7020及zYNQ芯片和开发有一个总体认识,为后面几部分的学习打好基础。第二部分是逻辑篇,在逻辑篇里我们把ZYNQ芯片当做普通的FPGA来使用,结合开发板和厶YNQ芯片的资源实现纯逻辑的开发。我们会通过大量的应用实例让大家了解和掌握FPGA的 Verilog程序的设计及实现。AX7010/AX7020开发平台的硬件资源。播下—粒种子,收获一片森林”,更是黑金 ALINX硬件开发的美好愿望,同时我们会在黑金动力社区http://www.hejin.org和大家一起讨论,一起学习,一起进步,一起成长。ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程目录序目录......4第一部分基础篇…第1章AX7010/AX7020开发板开箱检测.1.1准备工作.1.1.1硬件配置….112USB转UART驱动安装…1.1.3终端登录工具 Securecrt安装1.2外设连接141.3实验操作第2章zYNQ7000芯片的简介……172.1PS内部资源介绍……2.1PL内部资源介绍.….…19第3章 Vivado软件安装.31WⅣVADO软件介绍…。,乙3.2 VIVADO软件版本…033WⅣVADo软件安装21第4章Linuκ系统虚拟机的安装2941虚拟机的安装294.2安装 ubuntu30第5章PS和PL接口技术详解.4151AⅪ接口标准介绍4152zYNQ的AXI资源445.3P端的AⅪ接口设计……,455.4 AXI Interconnect.………第6章zYQ芯片开发流程的简介……4961开发工具介绍…4962开发流程说明……50第二部分逻辑篇52第7章 FPGA LED控制实验……5271硬件介绍.527.2创建工程537.3编写流水灯的 verilog代码….ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程74添加XDC管脚约束文件7.5编译7.6下载和调试…翻。着69第8章HDMI输出实验7381HDMI及TMDS原理738.2硬件介绍.758.3程序设计……/684添加XDC管脚约束文件798.5编译和下载80第三部分SDK篇81第9章 Hello world实验….18191 Vivado工程创建8192zYNQ系统的配置…9.3硬件导入SDK.9994SDK软件编程….10295下载和调试.,105第10章P端和PS端的协同设计流水灯实验110101 Vivado工程创建.110102zYNQ系统的配置11110.3添加XDC管脚约束文件….121104编译生成比特流文件122105硬件导入SDK12310.6SDK软件编程125107下载和调试…127第11章定时器中断实验131111中断控制器和计数器..131112zYNQ系统的配置13211.3硬件导入SDK.135113SDK软件编程..137114下载和调试…1D妻第12章按键实验..142121PS和PL共亨中断142122 Vivado工程创建…14312.3添加按键IP.……14512.4添加按键管脚约束15212.5编译生成比特流文件.153126硬件导入SDK153127SDK软件编程155ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程128下载和调试…161第13章自定义IP实验166131RTC时钟DS1302166132Vⅳvado工程创建.118133创建自定义IP134添加RTC管脚约束185135编译生成比特流文件…∴18513.5硬件导入SDK.186136SDK软件编程.186137下载和调试…189第14章VDMA实验硬件系统搭建….19314.1硬件构架193142搭建硬件工程…..….194143添加HDMI管脚约束…223144编译生成比特流文件…22414.5硬件导入SDK224第15章VDMA实验SDK软1件.225151SDK软件编程..225152程序说明22615.3图像数据生成方法…::::::::::::::.·t23154下载和调试235第16章程序固化和启动239161开发板启动流程239162 Vivado工程修改……163生成FSBL可执行文件….245164BOOT.BIN文件的生成165烧写 FLASH并启动254166SD卡启动257第17章 Linux开发环境的搭建………259171安装Lnu版本的SDK259172安装32位支持工具包270173安装 OpenSSL库第18章∪-boot的编译和启动.…273181∪-Boot原理及实现182∪-Boot的编译…279183生成 BOOTBIN文件283184 Uboot启动实验.295第19章内核的编译299ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程191 Linux内核介绍299192 Linux内核源码编译301193设备树 Device tree的编译.194文件系统第20章SD卡的制作20.1SD卡分区31020.2复制BOOT.BIN文件31420.3复制编译后的内核文件315204复制编译后的设备树文件·:..31520.5复制文件系统31620.6 Linux sd卡启动第21章 Linux系统下的 hello world实验…322211 nfs server安装和配置..322212编写 helloworld程序21.3编译 helloworld程序.33021.4运行……30第22章 Linux系统下的GPIO应用实践.332221 sysfs方式控制GPIO33222.2编写GPIO应用程序33622.3编译GPIO程序…:::::::::::·:340224运行和实验341ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程第一部分基础篇第1章AX7010/AX7020开发板开箱检测当我们拿到开发板是否应该测试一下收到的开发板是否功能正常,以及各个接口工作是否工作正常。在出厂前我们已经在SD卡里存储了启动程序和操作系统,所以开发板上电就能启动并可以用来测试各个部分接口和电路的工作是否正常。通过测试也使大家对我们开发板的功能有一个大致的认识。11准备工作1.1.1硬件配置开发板的上电检测需要以下的设备。其中SD卡里我们已经为用户存储了ARM的Boot启动程序和系统的镜像文件 lmage。红色USB线用于开发板和PC之间的串口通信。HDM线和HDMI显示器用于显示AX7010/AX7020开发板翰出的 Ubuntu界面,网线用于开发板连接 Internet网络,USB鼠标和键盘用于人机交互操作。因为开发板上只有一个USB口,这里需要连接一个∪ SB Hub设备来扩展多个USB口连接USB键盘和鼠标。AX7010开发板或AX7020开发板◇5V直流电源适配器(开发板自带)令 Micro sd卡〔开发板自带)mini usB数据线2根(开发板自带)今网线◇HDMI线和HDMI显示器◇USB鼠标和键盘r USB Hub◇PC机ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程下图为开发板自带的测试设备:S ZNO(1).AX7010/AX7020开发板;(2).SD卡读卡器;(3).+5V电源;④4).2根USB线;(5)SD卡下图为用户自己需要准备的测试设备USB Hub网线USB鼠标图图图图图图围图国园USB鼠标HDMI显示器ALⅠNX黑金mq700.列开发宏典http://www.heijin.orgALINXOALNX黑金2ynq7000开发平台配套教程112USB转UART驱动安装测试前我们需要安装∪SB转串口的驱动软件(05软件工具及驱动CP2l0 x Windows Drivers.zip),不然无法做串口通信测试。驱动安装好以后,用红色USB线连接电脑USB口和开发板上的∪ART口(7)进行连接,然后打开电脑的设备管理器,设备管理器能够找到串口设备CP210x,我机器上映射的是COM3。4端口(COM和LPTPH Silicon Labs CP210x USB to UART Bridge(COM311.3终端登录工具 SecureCrt安装终端工具有很多, putty, teraterm, Windows自带终端工具, SecureCRT等等,众多终端工具中,比较下来,还是 Securecrt最好用,我们在资料的05_软件工具及驱动 Securecrt目录下为大家准备了绿色免安装的 secureCRT软件。下面简单介绍基于 SecureCrT串口终端的创建(在后面串口终端打印启动信息,需要用到双击 Secure CRTexe图标112005/12/917:29应用程序打展273ORDER TXT2006/5/3113:30文本文档6README.TXT207/3/3013:51文本文档SecureCRT. CH2007/3/2111:57编译的HmL帮aaSecureCRT.EXE2007/4/81:12应用程序1.890sN. txt207/6/1115:03文本文档SSH2Client43. d1.2007//210:52应用程序扩展4663SSH2Core43.all2007/4/210:52应用程序扩展1,058第一次使用会弹出以下对话框,点击OKe CRTThis is the first time that you have runSecureCRT?. SecureCRT needs to set a folder wherefy a fol der belPressing Cancel will exit the application wi thoutsetting the confi gurati on folder.ADministrator App Data RoaninzlanDwke cOnf」C点击YES。ALⅠNX黑金mq700.列开发宏典10http://www.heijin.org
- 2020-07-01下载
- 积分：1
altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
- 积分：1
