Linux Shell 脚本攻略 中文 第三版和源码

①定义输出或输入为直流电能的旋转电机，称为直流电机，它是能实现直流电能和机械能互相转换的电机。 ②用PWM（Pulse Width Modulation）方式来控制转速；通过脉冲波输入的引脚来控制方向。 ③本实验中采用RF-310T-11400型号直流电机，同时配有光耦测速模块。通过检测输出脉冲来检测电机转速。 基于FPGA的直流电机/基于FPGA的直流电机 ├── dc1 │   ├── db │   │   ├── cmpr_kkg.tdf │   │   ├── dc1.(0).cnf.cdb │   │   ├── dc1.(0).cnf.hdb │   │   ├── dc1.(1).cnf.cdb │   │   ├── dc1.(1).cnf.hdb │   │   ├── dc1.(10).cnf.cdb │   │   ├── dc1.(10).cnf.hdb │   │   ├── dc1.(11).cnf.cdb │   │   ├── dc1.(11).cnf.hdb │   │   ├── dc1.(12).cnf.cdb │   │   ├── dc1.(12).cnf.hdb │   │   ├── dc1.(2).cnf.cdb │   │   ├── dc1.(2).cnf.hdb │   │   ├── dc1.(3).cnf.cdb │   │   ├── dc1.(3).cnf.hdb │   │   ├── dc1.(4).cnf.cdb │   │   ├── dc1.(4).cnf.hdb │   │   ├── dc1.(5).cnf.cdb │   │   ├── dc1.(5).cnf.hdb │   │   ├── dc1.(6).cnf.cdb │   │   ├── dc1.(6).cnf.hdb │   │   ├── dc1.(7).cnf.cdb │   │   ├── dc1.(7).cnf.hdb │   │   ├── dc1.(8).cnf.cdb │   │   ├── dc1.(8).cnf.hdb │   │   ├── dc1.(9).cnf.cdb │   │   ├── dc1.(9).cnf.hdb │   │   ├── dc1.asm.qmsg │   │   ├── dc1.asm_labs.ddb │   │   ├── dc1.cbx.xml │   │   ├── dc1.cmp.bpm │   │   ├── dc1.cmp.cdb │   │   ├── dc1.cmp.ecobp │   │   ├── dc1.cmp.hdb │   │   ├── dc1.cmp.logdb │   │   ├── dc1.cmp.rdb │   │   ├── dc1.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd │   │   ├── dc1.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd │   │   ├── dc1.db_info │   │   ├── dc1.eco.cdb │   │   ├── dc1.eds_overflow │   │   ├── dc1.fit.qmsg │   │   ├── dc1.fnsim.cdb │   │   ├── dc1.fnsim.hdb │   │   ├── dc1.fnsim.qmsg │   │   ├── dc1.hier_info │   │   ├── dc1.hif │   │   ├── dc1.map.bpm │   │   ├── dc1.map.cdb │   │   ├── dc1.map.ecobp │   │   ├── dc1.map.hdb │   │   ├── dc1.map.logdb │   │   ├── dc1.map.qmsg │   │   ├── dc1.map_bb.cdb │   │   ├── dc1.map_bb.hdb │   │   ├── dc1.map_bb.hdbx │   │   ├── dc1.map_bb.logdb │   │   ├── dc1.pre_map.cdb │   │   ├── dc1.pre_map.hdb │   │   ├── dc1.psp │   │   ├── dc1.root_partition.cmp.atm │   │   ├── dc1.root_partition.cmp.dfp │   │   ├── dc1.root_partition.cmp.hdbx │   │   ├── dc1.root_partition.cmp.logdb │   │   ├── dc1.root_partition.cmp.rcf │   │   ├── dc1.root_partition.map.atm │   │   ├── dc1.root_partition.map.hdbx │   │   ├── dc1.root_partition.map.info │   │   ├── dc1.rtlv.hdb │   │   ├── dc1.rtlv_sg.cdb │   │   ├── dc1.rtlv_sg_swap.cdb │   │   ├── dc1.sgdiff.cdb │   │   ├── dc1.sgdiff.hdb │   │   ├── dc1.signalprobe.cdb │   │   ├── dc1.sim.cvwf │   │   ├── dc1.sim.hdb │   │   ├── dc1.sim.qmsg │   │   ├── dc1.sim.rdb │   │   ├── dc1.simfam │   │   ├── dc1.sld_design_entry.sci │   │   ├── dc1.sld_design_entry_dsc.sci │   │   ├── dc1.sta.qmsg │   │   ├── dc1.sta.rdb │   │   ├── dc1.sta_cmp.8_slow_1200mv_85c.tdb │   │   ├── dc1.syn_hier_info │   │   ├── dc1.tis_db_list.ddb │   │   ├── dc1.tiscmp.fast_1200mv_0c.ddb │   │   ├── dc1.tiscmp.fastest_slow_1200mv_0c.ddb │   │   ├── dc1.tiscmp.fastest_slow_1200mv_85c.ddb │   │   ├── dc1.tiscmp.slow_1200mv_0c.ddb │   │   ├── dc1.tiscmp.slow_1200mv_85c.ddb │   │   ├── dc1.tmw_info │   │   ├── logic_util_heursitic.dat │   │   ├── mux_96e.tdf │   │   ├── mux_cqc.tdf │   │   ├── mux_m6d.tdf │   │   ├── mux_src.tdf │   │   ├── prev_cmp_dc1.asm.qmsg │   │   ├── prev_cmp_dc1.fit.qmsg │   │   ├── prev_cmp_dc1.map.qmsg │   │   ├── prev_cmp_dc1.qmsg │   │   ├── prev_cmp_dc1.sim.qmsg │   │   ├── prev_cmp_dc1.sta.qmsg │   │   └── wed.wsf │   ├── dc1.asm.rpt │   ├── dc1.bdf │   ├── dc1.done │   ├── dc1.fit.rpt │   ├── dc1.fit.smsg │   ├── dc1.fit.summary │   ├── dc1.flow.rpt │   ├── dc1.map.rpt │   ├── dc1.map.summary │   ├── dc1.pin │   ├── dc1.qpf │   ├── dc1.qsf │   ├── dc1.qws │   ├── dc1.sim.rpt │   ├── dc1.sof │   ├── dc1.sta.rpt │   ├── dc1.sta.summary │   ├── dc1.vwf │   ├── dcmotor1.bsf │   ├── dcmotor1.vhd │   ├── dcmotor2.vhd │   ├── dcmotor3.vhd │   ├── dcmotor4.vhd │   ├── dcmotor4.vhd.bak │   ├── incremental_db │   │   ├── README │   │   └── compiled_partitions │   │       ├── dc1.root_partition.cmp.cdb │   │       ├── dc1.root_partition.cmp.dfp │   │       ├── dc1.root_partition.cmp.hdb │   │       ├── dc1.root_partition.cmp.kpt │   │       ├── dc1.root_partition.cmp.logdb │   │       ├── dc1.root_partition.cmp.rcfdb │   │       ├── dc1.root_partition.cmp.re.rcfdb │   │       ├── dc1.root_partition.map.cdb │   │       ├── dc1.root_partition.map.dpi │   │       ├── dc1.root_partition.map.hdb │   │       └── dc1.root_partition.map.kpt │   ├── key_check.vhd │   ├── key_check.vhd.bak │   ├── mux1.vhd │   ├── rate.vhd │   └── xianshi.vhd └── 新建 Microsoft Word 文档.docx 4 directories, 146 files

Simplorer V9的培训资料，非常详细，一共407页的PDF，看完这个PDF，相信你已经是simplorer高手了。Conventions Used in this GuideGetting HelpAnsoft Technical SupportHelp MenuContext-Sensitive Help1. IntroductionOverview of the Simplorer Interface .........1-32. Creating a New ProjectAbout the three-Phase rectifier2-2Expected Results2-3Using Simplorer to Create and Improve the Design2-4Creating the new project2-5Add the New project2-5Rename the designAdd Design Notes(Optional)Save the New project2-73. Create the rectifier modelCreate the Three-Phase rectifier Schematic. 3-2Choosing, Placing, and Arranging Components onthe schematic she.3-3Connecting the Components3-8Defining Component Properties3-9Property Displays for Components3-13Specifying simulation Outputs.3-16Defining Solution Options and Analysis Parameters3-18Starting an Analysis3-19Plotting Rectifier Model Simulation Results3-204. Hysteresis Current-Controlled DC-Motor Start-UpModify the Rectifier Model Design.4-2Deleting the Resistive/Inductive Load,4-3Saving the sheet with a New Name4-3Place and Arrange the New Components4-4Connect the New Components.,,,,,,4-5Defining dc Machine valuesDefining Mechanical Load4-7Freewheeling Diode4-8Chopper Transistor4-8Controller Modeling using block elements..4-9Modifying Report Elements...4-11Display Diode CharacteristicDefining Simulation Parameters.4-13Starting Simulation(Block Components.4-13Simulation Results(Block Components)... 4-14Controller Modeling Using State Graph Components4-15Connecting the State Graph Components4-16Defining Properties of State Graph Components 4-Using Name References4-19Deactivating Components on the sheet4-19Starting Simulation(State Graph)...4-21Simulation Results(State Graph)4-225. Current and Speed Controlled Dc MotorModify the State graph design5-2Deleting the State GraphSaving the sheet with a New namePlacing and Arranging the New Block Componentson the sheet5-4Connecting the New ComponentsDefining Mechanical Load (Block)Defining the pl controller.........5-8Starting Simulation..5-12Adding a Rectangular Plot(Pl Controller)... 5-13Adjusting Plot Properties.5-14Checking the block Sequence..5-16Using Automatic Block Sorting5-16Using Manual Block Sorting5-16Rerun the Simulation(PI Controller)Simulation Results(PI Controller)5-176. Using VHDL-AMS Components forModelingVHDL-AMS Components,,,,.6-2Modify the pl controller Design.6-3Save the project with a new name6-3Delete the dc Machine component6-4Placing and Arranging the New VHDL-AMs Components on the sheet6-4Connecting the New VHDL-AMS Components 6-4Defining VHDL-AMS DC Machine values6-4Defining Connections for Machine Current..6-5Defining Simulation ParametersAnalyze and Display Simulation Results(VHDLAMS6-67. Variants of PWM ModelingPWM Modeling Overview7-2Create a New Project for the pWm models ..7-3Setting Initial ConditionsPWM Modeling Using EquationsDefining Simulation Parameters7-4Displaying Simulation Results with Reports 7-4Simulation results 7-6PWM Modeling with Equations and Time Function7-6PWM Modeling with State Graph Components 7-8Place and arrange the components on the sheet7-8Define Component properties翻国7-9PWM Modeling with Block Diagram Components 7Placing and Arranging the Components on theSheet7-118. Importing Legacy SchematicsTranslating a Legacy Schematic..8-2Importing the legacy Schematic8-2Starting an analysis...,,8-6Plotting Simulation Results8-7Estimated time tooplete this guide45 minutes

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