MATLAB 车牌识别

numpy-1.13.1+mkl-cp36-cp36m-win_amd64.whl Install numpy+mkl before installing scipy.

在2037年之前的任何Vivado版本（包括HLS、ISE、AccelDSP、System Generator、软硬CPU、SOC、嵌入式Linux、重配置等等功能）都可以永久破解，使用，使用本license文件时文件名不能有汉字和空格，在vivado2016.2 win7 x64及2014.4 win7 x86亲测可用

在java世界里目前充斥着各种框架，struts，spring……但究其根本还是离不开servlet，故鄙人从java最基础的servlet入手，研究如何不用框架但又利用框架的优势实现最简单的用户管理(增删改查，分页)，并使用到了ajax技术实现增删改查，分页完全不刷新，主要是为了改善用户体验

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

在ST官网申请的，花了好几天终于通过了，此文档为full版本的foc开源库，包含high frequency injection, MPTA, feed-forward，位置观测等功能。现在分享于大家，请放心下载使用。

基于STM32F103的PT100测温程序，通过pt100铂电阻与温度的线性性

这个一个基于SSH框架的简易网上书店系统，用户分为管理员和普通用户，管理员可以对图书增删改查操作，用户则可以查找书籍，加入购物车，查看购物车，清空购物车，结算购物车。------附有说明文档，代码均有注释，适合初学者。

modbus 是工业常用的通讯协议，原来是基于串口通讯的。后来随着TCP/IP的发展，出现了基于TCP的Modbus 这个源码就是基于TCP的modbus C#写的1.读 D0000 多个寄存器的值 00 00 00 00 00 06 09 03 00 64 00 07 PLC 回答 00 00 00 00 00 11 09 03 0E 00 00 FF BB 00 00 00 00 FF FF AB CD 00 00 06 06写 D0010单一 寄存器的地址 00 00 00 00 00 06 08 06 00 0A 00 08 00 00 00 00 00 06 08 06 0

【实例简介】简要介绍了AOS开发平台的入门，非常适合于初级开发者使用！

课程设计题目。实现了一般性的教学管理功能；偏向于实用。使用Access数据库。带注释，带实验文档、审核通过，填上姓名就可以直接上交的。