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A-Novel-Pilot-Decontamination
We have proposed a novel pilot decontamination scheme which combines the two existing schemes: SPRS and WGC-PD scheme.
- 2018-05-03 12:40:03下载
- 积分:1
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Genetic-Algorithm-in-OFDM-system
OFDM自适应资源分配时,我们知道遗传算法很常见,这里我们给大家编了一下遗传算法的代码,供大家参考(OFDM adaptive resource allocation, we know the genetic algorithm is very common here, we compiled a genetic algorithm code for your reference)
- 2012-03-06 09:55:52下载
- 积分:1
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vhdl1008
PCI slave IP core, in VHDL language ,has been verified,it is very easy to use.
it is an ideal IP to study PCI,design PCI Bridge
- 2020-06-18 18:20:01下载
- 积分:1
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rncludinc_including
基本的调制解调程序集(包括BPSK,QPSK,QAM,GMSK等) 基本的调制解调程序集(包括BPSK,QPSK,QAM,G(Basic modulation and demodulation assembly (including BPSK,QPSK,QAM,GMSK, etc.) basic modulation and demodulation assembly (including BPSK,QPSK,QAM,G))
- 2019-03-27 21:57:34下载
- 积分:1
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OPNET仿真的无线信道
OPNET仿真的无线信道,OPNET仿真的无线信道
- 2010-03-14 21:57:44下载
- 积分:1
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171751191208488
说明: 利用k分布的海杂波仿真matlab 程序(Sea clutter simulation)
- 2021-02-24 18:00:42下载
- 积分:1
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ddeclientvc
说明: DDE CLIENT,用于dde方式读区服务器内容(DDE Client for dde reading of server content)
- 2006-03-10 15:42:05下载
- 积分:1
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归档
对脉冲多普勒雷达的功能进行仿真,多目标,脉压,分辨率(matlab pd multi something useful)
- 2018-01-24 14:27:07下载
- 积分:1
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31121-4d0
3gpp关于usim应用测试指导规范,通用的,不光是td scdma(rd Generation Partnership Project
Technical Specification Group Core Network and Terminals
UICC-terminal interface
Universal Subscriber Identity Module (USIM)
application test specification
(Release 4)
)
- 2013-05-01 10:54:48下载
- 积分:1
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TheResearchAndIPDesignOfSMBusBasedSmartBattery
本文研究了SMBus
规范,介绍了典型的基于片上系统(SoC)设计的知识产权核(IP)实现,采用自顶向下
(Top-down)的集成电路设计方法完成了设计,并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真,顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)
- 2009-03-26 12:16:53下载
- 积分:1