(7,4)汉明码

五级流水CPU设计 流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器会写（WB）五级，对应多周期的五个处理阶段。一个指令的执行需要5个时钟周期，每个时钟周期的上升沿来临时，此指令所代表的一系列数据和控制信息将转移到下一级处理。(Five level flow CPU design)

基于quartus的布斯乘法器的verilog 实现。布斯乘法算法是计算机中一种利用数的2的补码形式来计算乘法的算法。该算法由安德鲁·唐纳德·布斯于1950 年发明，当时他在伦敦大学伯克贝克学院做晶体学研究。布斯曾使用过台式计算器，由于用这种计算器来做移位计算比加法快，他发明了该算法来加快计算速度。(The verilog codes of booth multiplier based on quartus. Booth multiplication algorithm is a computer algorithm using the complement form of number 2 to calculate the multiplication. The algorithm was invented in 1950 by Andrew Donald booth, who was working on crystallography at birkbeck college, university of London. Booth used a desktop calculator, and because it was faster to do shifts than to add, he invented the algorithm to speed up the calculations.)

完整的Verilog验证模型，包括设备完整的状态。(Complete verilog Verification Model)

verilog实现增量式PID算法，实测可用，带modelsim仿真(PID algorithm by verilog)

通过设置串口的波特率、起始位、检验位等参数，进行FPGA的串口通讯(By setting the baud rate, the starting bit, the test bit and other parameters of the serial port, the serial communication of FPGA is carried out)

通过随机数产生原理进行verilog编程，从而实现FPGA的随机数产生(Through random number generation principle for Verilog programming, so as to achieve the FPGA random number generation)

采用c语言生成chirp信号，m序列以及卷积函数(The chirp signal, m sequence and convolution function are generated by C language)

一个LTE的仿真代码，有些内容没写全，大体框架写了(ssdsdsdasdad)

ldpc verilog code has been descripted in this program

深度学习进行调制识别的数据集，用于卷积神经网络(dataset for cnn include generate_RML2016.04c and generate_RML2016.10a)