System-stabilization

数字信号处理中使用窗函数法设计线性相位高通FIR，性能良好(Digital signal processing using window function method to design linear phase FIR high-pass, good performance)

A JNI interface for ICU converters Source Code for Andriod.

本程序是用Q值法求得的关于席位的分配问题， 并对最结果进行了一定的考虑，是否公平，公平程度如何。(This program is to use Q value method about optimal seats, the allocation of And the results were certain consideration, whether fair, fair to what extent. )

相关法时延估计的matlab仿真，能对任意wave文件使用，并进行误差分析(Correlation time delay estimation of matlab simulation, can use any wave file and analyze the errors)

输入线性方程组的增广矩阵，运行就能求解出方程解~(Input linear equations augmented matrix, run out the equations can be solved ~)

its important for academic issues

CFAR一种门限设定方法，可以很好地对波动大的区域进行门限设定(CFAR of a threshold setting method, can be a good area for large fluctuations in the threshold setting)

用Boost做的多核集成算法，速度很快，精度很高(MKLBoost )

分别用普通构建方式和显示列表对物体进行绘制，实现各种复杂的交互控制(Were built with ordinary ways and display a list of objects to draw, to achieve a variety of complex interactive control)

在这项工作中,我们提出一个基于混沌的集成　　抖动升压电路用于多个振荡器抽样真的　　随机数发生器的架构。多个环形振荡器　　真正的随机数生成器需要大量　　戒指的积累内在抖动的逆变器　　有用的水平。因此,他们占领大的硅区域和消费　　大量的权力。该电路提供　　另一种方法推动使用混乱的抖动　　动态生成的两个环形振荡器的非线性耦合　　需要更少的组件的数量。的简单性　　提出了电路提供高集成和内在潜力　　面积和功耗低等优点。混沌动力学　　研究了电路的使用数值和电路　　模拟。测量测试芯片实现的结果　　250纳米CMOS技术(In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowled)