QPSK

matlab作聚类分析，可实现很好的分类效果哦(matlab for cluster analysis, can be achieved very good classification results oh)

基于灰色整定的PID控制在MATLAB中的源代码(Genetic Algorithm)

利用PSO算法求解分布式电源的选址定容问题，并考虑了分布式电源的随机性(Randomness of the PSO algorithm DG locating and sizing issues and considered the DG)

数据加密标准DES算法的Matlab实现 (NEWPNN- Designed probabilistic neural network SIM- on probabilistic neural network simulation)

说明：  加强环的应力和位移计算程序,可以求出每隔5度位置处圆环的应力\弯矩和位移.(strengthen the stress and displacement calculation procedures, we can solve every 5 degrees positions of the stress Circle \ moment and displacement.)

平面波与涡旋波的干涉产干涉条纹，条纹出现位错。(Plane wave and vortex waves produce interference fringes, stripes appear dislocation.)

最近学习OFDM用到的程序，仿真了DVB-T系统在2K模式下形成OFDM信号的过程(OFDM used recently to study the procedures, simulation of the DVB-T system in the 2K mode OFDM signal formation process)

描述一个潜入函数，说明了一个马尔科夫跳变系统在已知转移概率下的仿真 (Describe a dive into the function，illustrate a markov jump to change system known probability in transfer simulation )

A buffer with 2 inputs and 2 outputs is implemented in this experiment. The buffer has a buffer size k=6 cells for each input buffer, and arrival rate lambda, λ. The Matlab software was used to make this buffer. Two 2*2 arrays were created as two for inputs and outputs, a 2*6 array is created as the body of buffer. This means the buffer can hold the 6 data from two sources and the buffer has two input ports and two outputs port. However, it can only have one write or arrival for each input per slot time or cycle time and it can only have one read for each output per cycle time. We can only read out once per cell time from a given input buffer.(A buffer with 2 inputs and 2 outputs is implemented in this experiment. The buffer has a buffer size k=6 cells for each input buffer, and arrival rate lambda, λ. The Matlab software was used to make this buffer. Two 2*2 arrays were created as two for inputs and outputs, a 2*6 array is created as the body of buffer. This means the buffer can hold the 6 data from two sources and the buffer has two input ports and two outputs port. However, it can only have one write or arrival for each input per slot time or cycle time and it can only have one read for each output per cycle time. We can only read out once per cell time from a given input buffer. )

说明：  一组开发基于XILINX FPGA开发DSP算法的应用资料，具有实用性，可操作性。（3）(a group Xilinx FPGA-based DSP algorithm development of the information is useful, operability. (3))