PPPOEchangjianguzhangdaima

In this paper, we present and analyze efficient frame synchronization and frequency offset compensation scheme with ternary sequences for an orthogonal frequency division multiplexing (OFDM) system in Rayleigh fading channels. Frame synchronization is an essential procedure for normal operation of the OFDM system because of sensitivity to synchronization errors. And when there are frequency offsets in OFDM frame, the loss of orthogonality occurs and the interference problem among several subcarriers is introduced. These fact leads to the requirement for joint implementation of the frame synchronization and frequency offset compensation.

<应用WVD估计AM_FM信号的瞬时频率>,该文研究了应用WVD谱峰检测估计AM-FM信号的瞬时频率的方法及其性能。(< Application WVD estimate AM_FM signal instantaneous frequency> This paper studies the application of WVD peak AM-FM signal detection estimates the instantaneous frequency method and its performance.)

Cognitive Radio - Securuty

CCSDS推荐的LDPC编码方案，一系列参考标准，很好哦！(CCSDS recommended LDPC coding scheme, a series of reference standards, very good!)

文章涉及OTDM系统的实现，对研究此方向的同学有一定帮助(OTDM systems involved in the realization of the article, students in this direction of research will definitely help)

随机调制信号下的模拟ppm，结合PCA的尺度不变特征变换(SIFT)算法，包括主成分分析、因子分析、贝叶斯分析。( Random ppm modulated analog signal under Combined with PCA scale invariant feature transform (SIFT) algorithm, Including principal component analysis, factor analysis, Bayesian analysis.)

Adaptive Radio Resource Management for GSM using Neural Networks and Genetic Algorithms Ken Murray and Dirk Pesch Adaptive Wireless Systems Group

this is simply a report on the fading channel on different modulation scheme

汽车行业CAN通讯SAEJ1939标准英文版(Auto Industry CAN Communication SAEJ1939 Standard English Edition)

本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)