MATLABsimulationincommunication

关于polar codes的源码，简单的仿真。(An Brief Introduction to Polar Codes)

In this paper, we present and analyze efficient frame synchronization and frequency offset compensation scheme with ternary sequences for an orthogonal frequency division multiplexing (OFDM) system in Rayleigh fading channels. Frame synchronization is an essential procedure for normal operation of the OFDM system because of sensitivity to synchronization errors. And when there are frequency offsets in OFDM frame, the loss of orthogonality occurs and the interference problem among several subcarriers is introduced. These fact leads to the requirement for joint implementation of the frame synchronization and frequency offset compensation.

北斗卫星接口文件 北斗卫星导航系统 空间信号接口控制文件 （测试版） (Beidou satellite interface file Beidou satellite navigation system space signal Interface Control Document (Beta))

说明：  In order to solve the problem of low bandwidth utilization while the peak-to-average power ratio(PAPR) is reduced.

说明：  利用通信系统中调制信号的循环平稳特性,对频谱空洞进行检测,提升频谱感知技术在低信噪比下的性能。实验结果表明:与传统能量检测方法相比,采用循环特征检测方法改善了认知无线电中频谱空洞的检测能力。(Based on the cyclostationarity of modulation signals, spectrum hole is detected, aiming at the improve- ment of the performance of spectrum sensing in low SNR situation. The results show that comparing with the tra- ditional energy detection technique, cyclostationarity-based spectrum sensing technique has greatly improved the detective ability in cognitive radio.)

A simulator for wireless sensor networks using omnet ++ framework

APDL 培训资料，很好的学习ansys的资料(APDL training materials, information on good learning ansys)

无线网络中分集合并，包含原理，流程图，仿真图，源代码(Cooperative Diversity in Wireless Networks)

协作多点传输技术及其原理，对CoMP技术中的协作簇选择、CoMP用户划分、用户传输方案及预编码做出了介绍，通过仿真对比得到采用CoMP技术的系统性能增益(LTE CoMP Research)

本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)