This code is used for mpeg-2 encode,transform 188bit to 204bit(RS code)

vhdl code for carry lookahead addder

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

verilog开发FPGA，实现RS485串口通信(RS485 driver for FPGA )

轴系测试程序，多通道输入输出，实现时域、频域、轴心轨迹、瀑布图等功能。(Shafting test program, multi-channel input and output, to achieve time domain, frequency domain, orbit, waterfall and other functions.)

Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn

FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)

verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)

还好用，大家一起来看下，不错的图书管理软件啊 ，呵呵(Fortunately with, everyone look, the good library management software, ah, huh, huh)

CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)

说明：  用verilog编写的ddr3芯片读写控制程序，经过调试的，可以直接拷贝。已在Xilinx Spartan6 FPGA调试验证。(The ddr3 chip read-write control program written in verilog can be copied directly after debugging. Tested and verified on Xilinx Spartan6 FPGA.)