MAX II CPLD具有灵活的可编程接口，合并了分立的FLASH存储器件，能快速和容易地配置FPGA，DSP，ASIC等。本中文手册将让用户对CPLD有一个宏...

EUROPEAN STANDARD EN 50221 Common Interface Specification for Conditional Access and other Digital Video Broadcasting Decoder Applications-EUROPEAN STANDARD EN 50221 Common Interfa ce Specification for Conditional Access and ot her Digital Video Broadcasting Decoder Applic ations

myson mtv230-car tft 最新源程序-myson mtv230-car tft latest source

1. 完成时／分／秒的依次显示并正确计数，利用六位数码管显示； 2. 时／分／秒各段个位满10正确进位，秒／分能做到满60向前进位，有系统时间清零功能； 3. 定时器：实现整点报时，通过扬声器发出高低报时声音； 4. 时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整； 5. 闹钟：实现分/时闹钟设置，在时钟到达设定时间时通过扬声器响铃。有静音模式。 -1. Completed/min/sec display and correctly followed by counting, using six digital tube display 2. When/min/sec in the paragraphs of the correct 10-bit binary full, s/sub can do to advance the age of 60-bit, systematic function of the time cleared 3. timers: realize the whole point of time, by the time the level of sound from loudspeakers 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjustments 5. alarm clock: the realization of sub-/ when the alarm clock settings, settings in the clock arrival time ringing through the loudspeakers. There are silent mode.

本文结合公交查询系统的实际需要，通过对B/S模式、JDK开发环境及工具、Web发布服务、数据库以及SQL语言的深入学习及实践，主要完成了公交查询系统的需求分析、数据库设计、应用程序设计的工作。-Based Bus inquiry system to the actual needs, through B/S mode, JDK development environment and tools, Web services, database and the SQL language in-depth study and practice completed a major transit Query System requirements analysis, database design, application design work.

QPSK调制器的FPGA实现，提出了一种基于FPGA实现QPSK的方法-QPSK Modulator FPGA, presents a FPGA-based QPSK method of achieving

操作系统引导的一些介绍,对学习引导的有很大的帮助与提高-Guide the introduction of some of the operating system on the learning guide are of great help and improve

数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement is calculated under test signal within a certain period of time the number of pulses, which have a standard requirement by the divider gate time signal pulse counter records the number of signals from the controller to choose the gates and counters to make off synchronous control can be carried out.Controller based on the gate signal to determine the optimum range.

Random delay effect minimization on a hardware-in-the-loop networked control system using optimal fractional order PI controllers ⋆

描述了用CoolRunner CPLD实现mp3 player的一种方法，值得学习-Describes the CoolRunner CPLD with mp3 player realize a method, it is worth learning

VFP图书管理系统的课程设计报告，含有全部源码，和数据类型-VFP library management system curriculum design report, containing all the source code, and data types