TLC5615 FPGA(EP2C08)

利用SCCB和FPGA实现视频采集的论文，对相关开发人员具有很强的参考价值！ (FPGA implementation using the SCCB and video collection of the papers, the relevant developer has a strong reference value ! )

ISE环境下Verilog编程实现机械按键去抖(ISE Verilog programming environment under mechanical debounces)

模拟示波器的现实程序，有x，y和光标。采用AD5440输出，现实效果很好。（示波器x-y方式）(Analog oscilloscope reality program, there are x, y and cursor. Using AD5440 output, real good results. (Xy oscilloscope mode))

说明：  实现可连续输入数据做三角函数变换处理，通过verilog代码实现，(It realizes triangular function transformation for continuous input data.)

基于VHDL语言的串口发送和接收程序,自己调试通过，并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)

代码属于原创，写了一天，比网传的简单明了；用Verilog语言实现的IIC通信协议，用分频计数器的方法实现SCL的输出，同样用计数器的方式确定SCL的低电平中点，在此改变SDA的值。

基于 verilog的卷积运算代码，应用于离散小波分析。(verilog conv)

ISE 9.2 serials working

说明：  基于FPGA设计的一段测试VGA接口的VHDL小程序\功能为在显示器上间隔显示横条、竖条以及棋盘格等彩条信号，希望对初学FPGA驱动VGA接口的电子爱好者有用(FPGA-based design of a VGA interface VHDL test applet \ functions for the intervals shown in the display bar, vertical bars and checkerboard patterns and other signals of color, hope for beginners FPGA VGA interface driver useful for electronic enthusiasts)

说明：  DDS的基本原理主要由五部分组成，分别是；相位累加器，正弦波形存储器，数模转换器，低通滤波器和时钟，将相位累加器输出的数据作为地址，用来查询表的数据，将取出的正弦数据通过数模转换器输出模拟信号，模拟信号再通过一个低通滤波器输出纯净的正弦波信号。(The basic principle of DDS is mainly composed of five parts: phase accumulator, sinusoidal waveform memory, digital to analog converter, low-pass filter and clock. The output data of phase accumulator is used as address to query the data of table. The extracted sinusoidal data is output analog signal through digital analog converter, and the analog signal is output pure sine through a low-pass filter Wave signal.)