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软件无线电经典英文书籍《Autonomous Software
软件无线电经典英文书籍《Autonomous Software-defined Radio Receivers for Deep Space Applications》-software radio classic English books "Autonomous Software-defin ed Radio Receivers for Deep Space Applications "
- 2022-03-24 09:42:52下载
- 积分:1
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世界500强面试题
世界500强面试题-face the world"s top 500 questions
- 2022-07-15 09:59:18下载
- 积分:1
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胡广书数字信号处理书Fortran程序,包括书中全部信号处理算法。...
胡广书数字信号处理书Fortran程序,包括书中全部信号处理算法。-book on digital signal processing Fortran procedures, including book all signal processing algorithms.
- 2022-01-25 20:48:30下载
- 积分:1
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算法,很经典的一本书 中文名叫《算法概论》
算法,很经典的一本书 中文名叫《算法概论》-Algorithm, it is the classic Chinese book called " Introduction to Algorithms"
- 2022-03-22 02:24:51下载
- 积分:1
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NDIS under vista Programming Document, mainly describes the ndis filter (vista l...
vista下的ndis编程开发文档,主要描述了ndis filter(vista下推出的)和WFP,用来开发相应的底层网络程序,如防火墙-NDIS under vista Programming Document, mainly describes the ndis filter (vista launched under) and WFP, to develop appropriate procedures for the underlying network, such as firewall
- 2022-01-26 00:01:08下载
- 积分:1
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MFC Windows 程序设计 随书源码
MFC Windows 程序设计 随书源码-MFC Windows programming books FOSS
- 2022-09-13 16:30:03下载
- 积分:1
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《quantum cryptography》 pdf格式,《量子密码学》 2002年1月发行
《quantum cryptography》 pdf格式,《量子密码学》 2002年1月发行- Quantum cryptography pdf format, quantum cryptography in January 2002 Issue
- 2022-06-14 17:19:26下载
- 积分:1
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深入Java虚拟机
深入Java虚拟机-depth Java Virtual Machine
- 2022-11-14 22:35:09下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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集成电路经典教材主要内容是针对如何书写测试向量的
集成电路经典教材主要内容是针对如何书写测试向量的-IC is the main contents of the classic textbook on how to write test vectors of
- 2022-03-07 20:53:18下载
- 积分:1