TC下的图形库 v2.3

华为内部资料，绝对有用？希望对大家有用-huawei neibu peixun ziliao

这个源程序主要是针对C++的继承特性而写的，程序里面的解释很清楚。-This source is mainly for C++ inheritance characteristics of written procedures for the interpretation of which is clear.

MIMO-OFDM技术，以及算法仿真程序，空时编码，V-BLAST编码算法等。-MIMO-OFDM technology, and simulation algorithm, space-time coding, V-BLAST encoding algorithm.

关于windows api查询的文档 非常好的-inquiries on the windows api very good documentation

AT8000S Switch use Manual-AT8000S Switch Switch use Manual

Hyperlynx仿真介绍，其介绍了Hyperlynx仿真PCB的关键技术及实现细节，不可多得-HyperLynx Simulation introduction, the introduction of the HyperLynx PCB simulation technology and the key to realize the details of a rare

项目开发计划.rar- Project donor project rar

关于营销战略的思考 关于营销战略的思考 -on marketing strategy on the marketing of strategic thoughts on the marketing strategies of marketing for strategic thoughts on the marketing strategy of the marketing strategy of thinking

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

Intel C++编译器文档-Intel C compiler Documents