要在最低visual studio 2005的版本下运行，在运行后出现的对话框中输入密码就可以在下面的对话框中加密你想要加密的内容，可以保存加密后的内容，也可以...

对ORCLE数据库进行保护，具有很强的功能，有加密，访问，删除，等保护功能-right ORCLE database protection, and highly functional, encryption, access, deletion, such as the protection function

这个源程序向你介绍了怎样摆脱密码束缚的问题-the source to tell you how to shake off the shackles of password problems

My stuff is aimed at teaching, not efficiency. The others are probably much better implementations. The last one has both C++ and Java versions where my stuff is all C. So lots of choices!

这是我在学习Visual C++过程中做过的一个程序,可以作为大家学习Visual c++编程能力学习的参考,相信对读者会有所启发.-This is my learning Visual C conducted in the course of a procedure, As we can learn Visual Programming c learning ability of reference, I believe the readers will be inspired.

adfgx密表密码-adfgx secret password

软件模拟CRC冗余校验，可以对任意长度的发送序列求16位校验和，并且可以对接收序列进行检查。有详细的中文注释，和模拟函数-simulation software CRC Redundancy Check, for any length of this sequence for 16 checksum, and to be able to receive sequence for the examination. The Chinese have detailed notes and simulation function

这是一个编程开发用的AVI的播放器对初学者有启发作用-This is a programming using AVI player for beginners instructive role

本文介绍了在JAVA环境下如何实现IDEA对称加密算法。由于电子商务和电子政务的普及，安全加密技术在其中应用非常广泛，对安全加密技术的要求也很高。目前在JAVA环境下实现IDEA加密具有很多的优势，因为JAVA是基于面向对象的编程语言,并且由于它的平台无关性能被大量应用于Internet的开发。-This paper presents the Java environment IDEA how to achieve symmetric encryption algorithm. As e-commerce and e-government popular, security encryption technology, which is widely used for security encryption technology requirements is also high. In Java environment under IDEA encryption has many advantages, because Java is based on object-oriented programming language, and because it is platform independent performance was widely used in Internet development.

一个用VB写的壳！-write a VB shells!

While there are many AES cores around, this one is designed with LUT6 based FPGA architecture in mind from day one.  The AES Decryption Core for FPGA implements the decryption portion of the AES (a.k.a. Rijndael) algorithm described in the FIPS-197 specification. Key lengths of 128 / 192 / 256 bits are supported, each with a separate instantiation wrapper. Since the core is designed to take advantage of LUT6 based FPGA archit