基于EPM1270的PS2键盘鼠标驱动源码Verilog

用vhdl语言 来实现 四位并行加法器的功能 是本科生的必学内容-Using VHDL language to realize four parallel adder function is a must for learning the content of undergraduate

利用cordic实现三角函数的计算，用vhdl实现-use cordic achieve trigonometry calculations, using achieve vhdl

应用背景在本文中，我们提出了一种新的FPGAAES的S盒的利用高性能的实现减少素数的残留。这个该设计在Xilinx Virtex-5实现xc5vlx50 FPGA器件。目的是使用一种新的基于查找表的条目集渣盒素数。减少残留素S盒数量增加了更多的混乱，AES的整个过程算法，使其更复杂，并提供进一步抵抗攻击。我们的实现达到了3.09 Gbps的吞吐量，共采用了1745片一个Virtex-5 FPGA。关键技术AES的应用减少了素数剩余的设计基于S盒是用VHDL语言实现一个Xilinx Virtex-5 xc5vlx50（包：ffg676，速度等级：3）使用FPGA设计工具ISE 9.2i。表4FPGA实现结果表明AES减少残留的素数的S盒。它介绍了Xilinx公司的FPGA器件选择的目标，加密吞吐量实现，定时报告和整体设备利用率。

this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural -this project is based on 2*1 and 4*1 multiplexer and 1*2 and 1*4 demultiplexer using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering. Here dataflow techniques and behavioural

i2c总线的工程实现，可以用在altera环境下验证-i2c bus project implementation can be used in altera verification environment

stbc空时编码源码，非常好的程序。verilog程序-STBC Space-Time Coding Source, very good program. Verilog program

说明：  该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)

实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)

说明：  verilog语言编写的简单FPGA 的从机模式 spi 通讯(Slave mode SPI communication of FPGA)

VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6(Advanced Digital Design VerilogHDL_advanced_digital_design_code_Ch6Verilog HDL source CH6)