verilog 万能流水灯

fir filter 程序 老师上课留的作业，在这里跟大家分享一下，希望能有所帮助(fir filter procedures teacher in the class to stay the operation here to share with you, hope can be helped)

用Verilog实现的呼吸灯，用Verilog实现的呼吸灯(Verilog huxideng)

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

浙江大学体系结构实验课代码，5级流水线实现旁路和停顿(5-stage pipeline to achieve realization of the bypass pipeline bypass pause 5 pause)

Verilog code of SPI configurator for DAC AD7394 and AD7395

测量周期,此程序已经在EP2C板子上成功实现(mesure cycle)

This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.

VHDL code for converting BCD to Decimal

说明：  汉明码学习，以（7，4）为例，仿真正常。(Hamming code learning, taking (7, 4) as an example, the simulation is normal.)

该部分的主要功能是完成基于FPGA的polar码SC译码。(The main function of this part is to complete the FPGA-based polar code SC decoding.)