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华中科技大学计算机学院历届复试时上机考试试题与答案
华中科技大学计算机学院历届复试时上机考试试题与答案-, Huazhong University of Science Computer Science successive re-examination when the examination papers and answers on aircraft
- 2022-04-21 22:11:42下载
- 积分:1
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ASIC Design Flow Tutorial,讲解ASIC设计流程的超详细文档。
ASIC Design Flow Tutorial,讲解ASIC设计流程的超详细文档。-ASIC Design Flow Tutorial, explain the ASIC design flow, ultra-detailed documentation.
- 2022-04-29 03:34:34下载
- 积分:1
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计算流体力学非常经典的一本书,这么经典的书应该给大家分享一下!...
计算流体力学非常经典的一本书,这么经典的书应该给大家分享一下!-Computational Fluid Dynamics is one of the classic book, such a classic book should be given to share with you!
- 2023-02-28 04:05:03下载
- 积分:1
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关于JBOSS的,感觉比较好
就传上来,大家可以看看。
关于JBOSS的,感觉比较好
就传上来,大家可以看看。
- 2023-07-09 15:00:04下载
- 积分:1
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compiled with the help of language teaching document noted for
汇编语言的帮助说明加教学文件-compiled with the help of language teaching document noted for
- 2022-04-13 03:33:25下载
- 积分:1
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这是一个用c语言实现了实现区间数相关操作的程序,区间树具有动态创建和动态调整的特点,具有很多应用...
这是一个用c语言实现了实现区间数相关操作的程序,区间树具有动态创建和动态调整的特点,具有很多应用-This is a language used to achieve the realization of c interval number associated operating procedures, with a dynamic range of the tree to create and adjust the dynamic characteristics, with many applications
- 2022-03-01 13:24:36下载
- 积分:1
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html语法教学,主要介绍html中的各种标签的使用,非常的实用
html语法教学,主要介绍html中的各种标签的使用,非常的实用-html grammar teaching, mainly on the various html label use, very practical
- 2022-10-25 18:05:03下载
- 积分:1
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包含了很多基本的c程序,其中有很多可以直接在VC中运行
包含了很多基本的c程序,其中有很多可以直接在VC中运行-C contains a lot of the basic procedures, many of which can be run directly in the VC
- 2022-05-20 02:07:19下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1
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一个功能精简的TCP/IP协议栈,实现的基本功能,对研究协议也有帮助...
一个功能精简的TCP/IP协议栈,实现的基本功能,对研究协议也有帮助
-a function to streamline the TCP/IP protocol stack, to achieve the basic functions of the research agreement will be of help
- 2023-04-16 20:45:03下载
- 积分:1