verilog hdl verilog hdl verilog hdl

CAN RTL级设计,详细介绍了符合CAN协议的芯片级设计。-Design of CAN RTL level

学习ＦＰＧＡ的好文章，从中可以了解到如何实现ＦＰＧＡ最小系统-Learning FPGA good articles, which can learn how to achieve the smallest FPGA system

学生作业管理系统设计文档，有关于各个不同部分的详细介绍-Student Activity-Based Management system design documents, on the detailed description of the various different parts of the

续--基于Wed技术的通用监控平台设计方案--以互连网为核心的技术革命，正给人类工作、生活，乃至生存带来巨大变化。如何将已有的应用系统与蒸蒸日上的互连网技术结合起来，进一步提高企业的运作效率和企业形象，得到了企业的广泛关注。SCADA系统在工业智能自动化领域为广大用户提供了优秀的服务，随着互连网技术的发展和应用，为了进一步满足客户的需求，公司提出将现有的IA系列产品SCADA与Web技术有机结合起来，实现基于Web技术的SCADA监控平台-Continued- Wed technology based on a common platform for the design of monitoring programs- to the Internet as the core of the technological revolution, is to the human work, life, and even bring about great changes in survival. How to existing application systems and the success of the combination of Internet technology to further enhance the operational efficiency and corporate image, has been widespread concern in the enterprise. SCADA system in the field of intelligent automation industry to provide customers with excellent service, with the development of Internet technology and applications, in order to further meet customer demand, the company proposed to the existing SCADA and IA products combine Web technology , Web-based SCADA monitoring platform

基于ＬＡＢＶＩＥＷ主菜单的设计方法，详细介绍了菜单设计过程-LABVIEW-based main menu design method, described in detail the design process menu

采用ARM和FPGA组合，共同实现电脑横机控制器-The use of ARM and FPGA combination of a common computerized flat knitting machine controller

信息系统设计文档，介绍报告的格式，内容等相关信息-Information system design documents, introducing the report, the format, content and other related information

厦门亿宝大厦PHS室内覆盖系统设计-Xiamen billion-building PHS indoor coverage system design

数字频率计的设计可以分为测量计数和显示。其测量的基本原理是计算一定时间内待测信号的脉冲个数，这就要求由分频器产生标准闸门时间信号，计数器记录脉冲个数，由控制器对闸门信号进行选择，并对计数器使能断进行同步控制。控制器根据闸门信号确定最佳量程。-The design of digital frequency meter can be divided into measurement and display count. The basic principle of its measurement is calculated under test signal within a certain period of time the number of pulses, which have a standard requirement by the divider gate time signal pulse counter records the number of signals from the controller to choose the gates and counters to make off synchronous control can be carried out.Controller based on the gate signal to determine the optimum range.

该论文以CAN总线的实时性问题为研究对象，在系统分析了CAN总线协议的特点并指出CAN总线的主要局限性的基础上，对CAN总线网络通信的实时性问题进行理论分析。 -CAN bus to the paper issues real-time study in the analysis of the characteristics of CAN bus protocol and pointed out that the main limitations of CAN bus based on CAN bus network communication theory in real-time analysis of issues .