verilog hdl verilog hdl verilog hdl

实时钟 实时钟 -Real Time Clock Real Time Clock Real Time Clock Real Time Clock

本文基于遗传算法思想，采用浮点数矩阵表示编码，在遗传算法的进化过程中加入一定的约束条件等方法，探讨了网络结构的设计和学习。经实例分析，在用于建立大坝安全监控预报模型的前馈神经网络设计中，该方法在满足一定约束条件下，能同时有效地寻找合适的网络结构和相应的参数(神经网络的权值和阈值)，且在精度和速度上都有较大的提高，为实现实时在线分析评价大坝的安全性态提供了有力的技术支持。-Based on the genetic algorithm, using a float matrix coding, Genetic algorithms in the evolutionary process to be bound by certain conditions, to explore the structure of the network design and learning. By analyzing the examples used in the establishment of dam safety monitoring forecasting model of neural network design, The constraint in meeting certain conditions, can effectively find suitable network structure and the corresponding parameters (the neural network weights and thresholds), and the accuracy and speed have improved greatly. To achieve real-time online analysis and evaluation of the safety of the dam states provide strong technical support.

Document For The Sinewave Inverter

JAVA编写的SOCKET通信 客户端案

DVB Document A053 Extensions to the Common Interface Specification

GPS车辆监控调度系统的设计方案-GPS vehicle monitoring system design scheduling program

This document related to CBIR - Content Based Image Retreival System. Average RGB concept is used.-This document related to CBIR- Content Based Image Retreival System. Average RGB concept is used.

CH341 general usb-serial/pp interface.specification document -CH341 general usb-serial/pp interface.specification document

This program would work fine only with a specific flash tool through PC printer port under EPP mode.Program is capable of identifying flash chip manufacturer, device type, capacity,... It also allows user to dump flash data, edit/revise the content of flash chip on the Screen, and re-write them back to the chip.

MATLAB用于自动化设计，该系统为我们的一个期中作业题，从中可以巩固自动化的知识。-MATLAB for design automation, the system for a period of our operations that, We can consolidate automation knowledge.