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This is a good book about mathematics and gives listing code also for various al...
This a good book about mathematics and gives listing code also for various algorithms-This is a good book about mathematics and gives listing code also for various algorithms!!!
- 2022-03-04 18:11:38下载
- 积分:1
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This book introduces the Altera s soft
本书主要介绍Altera公司的软核CPU――nios和采用该CPU进行嵌入式系统设计的流程与方法。并以此为着眼点,介绍Altera的片上可编程系统SOPC的设计原理与实践技术,引领读者在低投入的情况下,较快地进入片上系统soc的殿堂。
-This book introduces the Altera s soft-core CPU- nios and the use of the CPU for embedded system design process and methods. As the focus on Altera s programmable system chip SOPC design principle and practice of technology, leading the reader in the case of low-input, fast access to system-on-chip soc hall.
- 2023-03-09 21:10:04下载
- 积分:1
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win32系统编程3,内容有点深 johnson M.Hart著
win32系统编程3,内容有点深 johnson M.Hart著-3, as a little deep with johnson M. Hart
- 2022-02-03 12:37:38下载
- 积分:1
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世界名著封神演义大作。
世界名著封神演义大作。-masterpiece of world literature Senior Life Romance NPC.
- 2023-08-06 20:45:04下载
- 积分:1
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C dialogue classic series, read on to know, I do not to say more, because it is...
C++经典对话系列,看了就知道,我就不多说啦,反正是好东西啦!-C dialogue classic series, read on to know, I do not to say more, because it is good stuff!
- 2022-02-07 17:14:56下载
- 积分:1
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java极限编程书籍,自己是才鸟,不懂穿上来和大家一起研究
java极限编程书籍,自己是才鸟,不懂穿上来和大家一起研究
- 2022-01-25 15:52:05下载
- 积分:1
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本电子数为比较经典的《数据结构及其算法集》,作者为高一凡,比较详细的介绍了各种算法。...
本电子数为比较经典的《数据结构及其算法集》,作者为高一凡,比较详细的介绍了各种算法。-In order to compare the electronic digital classic
- 2023-05-27 03:00:04下载
- 积分:1
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java初学者实践
java初学者实践 -java beginner practice.,,,,,
- 2023-03-27 13:45:04下载
- 积分:1
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顾准的日记,一代大师的心迹
顾准的日记,一代大师的心迹-Guzhun"s Diary, I feel great master
- 2022-12-07 06:45:03下载
- 积分:1
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FPGA pipelined designs on paper This work investigates the use of very deep pipe...
关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work invest
- 2022-11-28 12:05:03下载
- 积分:1