讲述PC的原理技术，包括cpu与内幕指令、系统与设备检测、适配卡开发，bios数据、cmos与时钟、DMA服务等...

flash杂志制作软件，简单易用，功能强大。-flash magazine production software, easy-to-use and powerful.

Naranda Pali Course. Introduction to learning Pali language

eclipse使用方法详解，对于初学eclipse的人会有很大的帮助-Detailed use eclipse for eclipse beginner people will be very helpful to

Dan Saks关于const的所有用法-Dan Saks talks about the usage of const

上传的是是学习xml的一个很好的教程，简单易学，可以一看-Upload is learning xml a good guides, easy, one can see

Microsoft C Language Concise

高质量C编程指南,林锐博士编.-quality C programming guides, LIN Dr. series.

一个不错的时序电路逻辑设计与特殊组合函数-a good sequential logic circuit design and function combination special

图灵Ajax三剑客：《Ajax基础教程》、《Ajax实战》、《Ajax高级编程》的源代码-Turing Ajax Three Musketeers : "Ajax basis Guide", "Ajax real," "Ajax Advanced Programming" source code

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest