飞思卡尔MC9S12XET，SPI程序

基于sy2100 ez-usb开发板的程序-BASE IN SY2100 EZ-USB develop board program

lpc22xx系列arm的i2c驱动,并且包含zlg7290的应用.详细使用方法见程序文档-lpc22xx series arm of the i2c driver, and includes zlg7290 applications. detail see the use of program documentation

一个基于minigui写的通讯录模块，还有完善空间-Minigui-based address book written in modules, as well as improve the space

原始数据以Kiwi格式存储在GTBL.dat的二进制文件中，具体的文件格式请参照ReveseTableFormat.xls 中的“逆引表格式”sheet.-this procedure is the function of the navigation data of the road data collation, analysis. Kiwi to the original data stored in the format of the binary file GTBL.dat, specific file format ReveseTableFormat.xls Please refer to the "reverse primer format" sheet. -Kiwi original data format is stored in binary file GTBL.dat, the specific file format ReveseTableFormat.xls Please refer to the

基于S3C2440 对 K9F1208 Nand Flash 的读写,取自uboot,对其进行了修改-S3C2440 based on K9F1208 Nand Flash reading and writing, from uboot, its modified

lwIP是瑞士计算机科学院（Swedish Institute of Computer Science）的Adam Dunkels等开发的一套用于嵌入式系统的开放源代码TCP/IP协议栈。Lwip既可以移植到操作系统上,又可以 在无操作系统的情况下独立运行.-lwIP Switzerland Computer Sciences (Swedish Institute of Computer Science), Adam Dunkels such as the development of a set of embedded systems for the open source TCP/IP protocol stack. Lwip can migrate to the operating system, can in no circumstances the operating system operate independently.

AVR单片机内部EEPROM实验， 学习AVR单片机的内部的EEPROM的读写-failed to translate

资源描述对51单片机的基础运用，本人第一次上传代码，请多多指教

共享软件注册算法的研究与设计，分析当前流行的一些软件保护技术；研究各种共享软件的注册算法；并且设计一个好的软件注册算法。一个好的软件注册算法，可以实现对软件作者的知识产权的有效保护，促进共享软件的发展。- Design and Research of Share Software Registration Arithmetic

由 Xilinx 提供的 IIC 接口，使用 AXI interface。 Features ‧ AXI interface is based on the AXI4-Lite interface ‧ Master or slave operation ‧ Multi-master operation ‧ Software selectable acknowledge bit ‧ Arbitration lost interrupt with automatic mode switching from master to slave ‧ Calling address identification interrupt with automatic mode switching from master to slave ‧ START and STOP signal generation and detection ‧ Repeated START signal generation ‧ Acknowledge bit generation and detection ‧ Bus busy detec ‧ Fast mode 400 KHz operation or standard mode 100 KHz ‧ 7-bit or 10-bit addressing ‧ General call enable or disable ‧ Transmit and receive FIFOs - 16 bytes deep ‧ Throttling ‧ General purpose output, 1 bit to 8 bits wide ‧ Dynamic Start and Stop generation ‧ Filtering on the SCL and SDA signals to eliminate spurious pulses