串口调试助手

sample drivers source code

DVB数字机顶盒中CA的通用接口源代码和通信数据格式分析。采用C编写-The source code written in C language for general interface of CA ,which is used for DVB digital SET top box ,and analysis about communication data.

这是一个简单的 vhdl 代码计数器与 synthesizeble xilinx ise 项目。它是一个四位计数器用于 xilinx 斯巴达 6 lx9 fpga 上 sparten 6 lx9 microboard 实施测试。

在数字电路的设计中，时序设计是一个系统性能的主要标志，在高层次设计方法中，对时序控制的抽象度也相应提高，因此在设计中较难把握，但在理解RTL电路时序模型的基础上，采用合理的设计方法在设计复杂数字系统是行之有效的，通过许多设计实例证明采用这种方式可以使电路的后仿真通过率大大提高，并且系统的工作频率可以达到一个较高水平-In digital circuit design, timing design is a main indicator of system performance in high-level design methods, control of timing was also a corresponding increase in the abstract, so more difficult to grasp in the design, but in understanding the RTL circuit timing model based on rational design methods used in the design of complex digital systems is a well-established through many design examples prove that this approach can make the circuit after the simulation significantly improve pass rates, and the system operating frequency can reach a high level

基于51单片机的程序设计，资料的详细功能、包含内容说明-51 MCU-based programming, the information detailed features, including the content description

用verilog写的基于cpld的交通灯控制器的源代码，供参考-Use verilog to write cpld-based traffic signal controllers and the source code for reference

gb2312转换 gb2312转换 gb2312转换-gb2312changechange

ce ftp客户端-ce ftp client

zigbee CC2500_sample_code.zip

一个完整DVDROM代码(使用日立PICKUP)-a complete code (using Hitachi PICKUP monitor)