32位浮点乘法verilog HDL

Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.

利用VHDL语言描述出一个双脉冲，可任意设置两脉冲长和中间时间间隔。(A double pulse is described in VHDL language, and the two pulse length and the intermediate time interval can be arbitrarily set.)

流水灯在Verilog语言下的分模块设计。分别是时钟脉冲+计数器+LED控制

它是利用FPGA实现OFDM系统的整体设计，包括两部分，一部分是发射机，另一部分是接收机。

使用verilog编程对ram进行读写，用8位地址控制8位宽的数据进行存储。

关于SPWM调制设计VHDL代码 关于SPWM调制设计VHDL代码(SPWM modulation on the design of VHDL code design on the VHDL code modulation SPWM)

滤波器的实现，总共为4种，是简单的coif3滤波器的实现方法(The implementation of the filter, a total of 4, is a simple coif3 filter implementation method)

this is a vhdl program...

LCD Interface_Xilinx.CPLD源码参考设计(LCD Interface Xilinx CPLD)

基于System Generator的图像处理工程,多媒体处理FPGA实现的源码,基于视频的运动跟踪(System Generator based image processing engineering, multimedia processing on FPGA source, video-based motion tracking)