AHB slave SRAM module

联邦滤波法，毕设时写的，可以和其他方法的做比较(Kalman filter, write the complete set up, and other methods to compare)

本实验为UART回环实例，实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx，以及时钟产生模块clk＿div。uart＿rx将收到的包解析出8位的数据，再传送给 uart_tx发出，形成回环。参考时钟频率为100MHz，波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)

本程序是本人按照教程一步一步生成的，内部有textbench可以进行仿真验证。

Altera大学计划程序包，基于Nios II的源代码(Altera University program package, based on the Nios II source code)

本例介绍直接合成带阻滤波器的方法，n阶滤波器能实现n个传输零点(A direct synthesis technique of a new class of bandstop coupled resonator elliptic filters is presented. Two different coupling schemes, which both include source–load coupling are used. The first coupling and routing scheme is the standard folded structure used in implementing bandpass elliptic filters with transmission zeros using resonators.)

Matlab agc ʵ

DAC0832的Verilog代码，适用于与ADC0809同时学习，效果明显！(DAC0832 Verilog code, applicable at the same time with ADC0809 learning, the effect is obvious!)

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

8级cordic 算法verilog (8 cordic algorithm verilog)

FPGA编写环境，具有仿真容易，软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)