一个基于fpga的源程序，对于初始接住的人来说很有帮助

FIFO的verilog描述(Verilog description of the FIFO)

SRIO接口物理层的实现代码，非常复杂，完全自己用verilog编写，支持5G速率，可以作为开发参考(SRIO interface implementation code, the physical is very complex, completely written in verilog, support rate of 5 g, will be helpful to the development)

说明：  misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)

xilinx FPGA 与高速ADC LVDS接口的范例程序(xilinx FPGA ADC LVDS interface)

说明：  千年服务端修改工具，千年db数据在线修改(Millennium server modification tool Millennium server modification tool)

VHDL语言基本数学运算库-VHDL basic arithmetic library

说明：  串口操作源代码，本代码采用veilog hdl语言编写，并经过本人多次验证。(source code, the code used veilog HDL language, and after I repeatedly verified.)

基于FPGA的VGA控制器，可在屏幕显示彩色条纹(A vga controller based on FPGA)

本程序实现流水线功能，您可根据自己需要更改参数，试用芯片xilinx，用verilog语言编写(This program implements the pipeline, you may be required to change the parameters according to their own try xilinx chip with verilog language)

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