verilog HDL语言的综合实验

伪随机LED灯，实现八位LED灯的随机闪烁以及其它的控制。(Pseudo-random LED lamp)

说明：  ? 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。 ? 利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。 ? 利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。 ? 利用双线性插值方法实现对图像640×480到1024×768的放大操作。 ? 完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format. Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface. With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA. The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768. Complete the VGA display interface design.)

功能说明：实现倒计时、按键可实现暂停/继续、时间设置、清零 附加说明：倒计时到零时，蜂鸣并闪烁；暂停时，时间分隔符闪烁；设置时，当前设置位闪烁。  按键说明  非设置状态：      数字显示不为0时，按enter键在计时与暂停状态进行切换，长按秒进入设置状态，长按5秒清零并进入暂停状态;  全为零时按enter键进入设置状态;  设置状态：      按enter进入计时状态  长按一秒置零  长按5秒置零并进入暂停状态   

找到这本书的完整版了。呵呵，贴出来和大家共享。这是本好书，我买了一本作为Verilog的参考书。这本书语法部分集中，便于查阅，此外讲了很多实用的设计思想。最重要的是本书薄，可以完整看完。强烈推荐。 （如果只是查阅，电子版就可以，如要完整学习，建议还是买纸质版的）(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))

5阶数字滤波器 使用了coregenerator产生的multiplier，这个应该是最节省资源的方式了

This is the update firmware for CVFX-C02, 7" motorized touch screen car dvd player gps

verilog编写的uart发送模块，起始位，数据位，可选择的奇偶校验位，停止位。仿真可用

verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)

802.11a的基带分组检测的verilog实现，其使用了分组检测的优化算法——延时相关保存算法，具有由于的检测性能。

讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form )