高效STL编程，STL编程的经典之作，相信GP编程高手一定知道它。...

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

JPEG2000分数位平面编码器的fpga电路实现-scores bitplane JPEG2000 encoder circuit of fpga

2003年各大论坛最具影响力的照片电子书-2003 major forum of the most influential photo e-books

TMS320C6000与UART的通信,提供了两种解决办法.-TMS320C6000 and UART communications, the two solutions.

《C++程序设计实验指导与实训》源代码-"C Programming Training experimental guidance and the" source code

jsp学习文章很好-jsp good learning article

SIP的RFC文档。RFC3621. RFC3621-SIP RFC documents. RFC3621. RFC3621

VBA For Word 2002 资料-Word 2002 VBA For information

我学习UNIX的体会。-I learn UNIX experience.

java学习 学习好资料 数据结构与算法（JAVA语言版） 数据结构与算法（JAVA语言版）-java learn good data structure and algorithm (JAVA language version) Data Structures and Algorithms (JAVA language version)