本文基于ARM7嵌入式系统对USB接口装置的发展

具体内容见文章，主要是研究小网络世界的动态耦合同步-See the specific contents of the article is to study the dynamics of small-world coupling network synchronization

Mvref routing on a wirebond package

基于ISO_IEC15693协议的射频识别系统设计-ISO_IEC15693 agreement based on Radio Frequency Identification System Design

自己收集的关于协同分集的资料，请大家多多参考-own collection of the synergy at the data collected, please refer lot

virtual reality project. This algorithm for building large image to Volume rendering. Using directx

IEC61000 International Standards

这篇文章是对当前IEEE中的最新的无线传感器网络的新发展和新动向进行预测和说明

fluent 燃烧方面的英文PPT,学习参看用-combustion fluent in English PPT, see with learning

This paper introduces an affine invariant of trapezia, and the explicit constraint equation between the intrinsic matrix of a camera and the similarity invariants of a trapezium are established using the affine invariant. By this constraint, the inner parameters, motion parameters of the cameras and the similarity invariants of trapezia can be linearly determined using some prior knowledge on the cameras or the trapezia. The proposed algorithms have wide applicability since parallel lines are not rare in many scenes. Experimental results validate the proposed approaches. This work presents a unifying framework based on the parallelism constraint, and the previous methods based on the parallelograms or the parallelepipeds can be integrated into this framework. Key words: invariant parallelism constraint camera calibration 3D reconstruction

现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、Cache等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ＲＯＭ以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明，这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length.