大型设计中FPGA的多时钟设计策略,很详细的描述了在FPGA设计中时钟设计的方法...

infra red mouse source code

DDS发生器NIOS .c文件,在NIOSII中可以配合Verilog代码生成的自定义外设产生DDS信号-DDS generator NIOS. C files, NIOSII can be in Verilog code generation with custom peripherals DDS generated signal

用在palm上的黑白棋，带人机对战功能，适用在palm os 3.5以上操作系统-with the palm of reversi, with human-computer screen, suitable for the above palm os 3.5 operating system

EDA高手入门必看，FPGA-CPLD-开发流程。-EDA players see entry, FPGA-CPLD-development process.

ISP for STR73X 默认情况下, bank0 是映射到地址0x00. 考虑到,IAP程序需存储在bank1,而用户程序需存储在bank0. 因此须使用CAPS工具,将bank1映射到地址0x00. 另外, 在IAP程序运行期间,必须在执行用户程序跳转之前,通过程序将bank0重映射到地址0x00(注:IAP程序已经实现了bank0重映射到地址0x00,用户不需要自己来编写代码).-ISP for STR73X default, bank0 is mapped to address 0x00. Taking into account, IAP process is stored in the bank1, while the user program to be stored in bank0. It is necessary to use the CAPS tool bank1 mapped to address 0x00. In addition, IAP procedure during operation must be in the implementation of user program before Jump through the procedure will bank0 re-mapped to address 0x00 (Note: IAP program has achieved bank0 re-mapped to address 0x00, the user does not need to write their own code).

单片机课程实验，微机接口实验程序源码 包括8088等芯片-Singlechip course experiments, computer source interface Experimental procedures including the 8088 chip, etc.

为C8051F005制作的网络模块--Network module for C8051F005.

timer full program for avr atmega 16

温度传感器18B20的keil C51驱动程序-temperature sensor 18B20 the keil C51 Driver

一个很不错的无线传感网络协议栈，特别适合初学者-A very nice wireless sensor network protocol stack, particularly suitable for beginners